DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed on 12/26/2023, 06/28/2024 and 10/15/2024 has been considered and placed in the application file.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-5 and 10-24 are rejected under 35 U.S.C. 103 as being unpatentable over Wenske (U.S. 2023/0091219).
Regarding claim 2, Wenske (hereinafter, Ref~219) discloses (please see Fig. 1-4 and related text for details) a method for clamping (e.g., via clamping features provided by 162 of Fig.1 and/or 412 of Fig. 4 as discloses in paragraph 0052) an output (e.g., VOUT of Fig. 4) of an amplifier (see 400 of Fig. 4), the method comprising:
coupling a current limiter (128 and/or 148 and/or 130 of Fig. 4 can be read as the claimed limiter OR at least it is functionally equivalent to it, since it is configured to adjust current for the input stage and/or the output stage based on the said clamp circuit 412 of Fig. 4) in series-connection with a first conduction path of a first stage (129 of Fig. 4) of the amplifier;
sensing (via M15N of Fig. 4) a voltage at a sensing node (gate of M12N of Fig. 4) of the amplifier; and
based on the sensing, controlling the current limiter to limit a current through the first current conduction path, wherein the voltage at the sensing node of the amplifier controls a current through a second current conduction path (IOUT of Fig. 4) of a second stage (centered by 134/136 of Fig. 4) of the amplifier, meeting claim 2.
Regarding claim 3, Ref~219 discloses the method according to claim 2, further comprising: providing an input (disposed at gate of 134/136 of Fig. 1) to the second stage via the first stage as seen from Fig. 4, meeting claim 3.
Regarding claim 4, Ref~219 discloses the method according to claim 3, further comprising: implementing the second stage as an output stage of the amplifier as seen from Fig. 4, meeting claim 4.
Regarding claim 5, Ref~219 discloses the method according to claim 2, wherein:
the voltage at the sensing node is based on a magnitude of a current that flows through the first current conduction path of the first stage, since the current flows through the first current conduction path of the first stage inherently affects the output voltages, namely VPshift/VNshift, output from the input stage and said output voltages being provided to said second stage, meeting claim 5 .
Regarding claim 10, Ref~219 discloses the method according to claim 2, further comprising: implementing a clamp sense circuit (412 of Fig. 4) via a replica circuit (M15N of Fig. 4) of the second stage of the amplifier;
coupling the clamp sense circuit to the sensing node; and
sensing the voltage at the sensing node via the clamp sense circuit as seen, meeting claim 10.
Regarding claim 11, Ref~219 discloses the method according to claim 10, further comprising: based on the controlling of the current limiter, further limiting the current through the second current conduction path (by adjusting the gate voltage of 134 of Fig. 4), meeting claim 11.
Regarding claim 12, Ref~219 discloses the method according to claim 10, wherein:
the replica circuit is a reduced-size replica of the second stage, since ISENSE is a scale version of IOUT as described in paragraph 0022. In addition, these are normal design parameters/features in the field depending on custom specifications, meeting claim 12.
Regarding claim 13, Ref~219 discloses the method according to claim 10, further comprising: providing an input to the second stage via the first stage as seen from Fig. 4, meeting claim 13.
Regarding claim 14, Ref~219 discloses the method according to claim 13, further comprising: implementing the second stage as an output stage of the amplifier as seen, meeting claim 14.
Regarding claim 15, Ref~219 discloses the method according to claim 10, further comprising: implementing the second stage via a common-source FET transistor (134 of Fig. 4) in series- connection with a current source (126 of Fig. 4); and
implementing the replica circuit via a reduced-size common-source FET transistor in series-connection with a reduced-size current source as expected, since ISENSE is a scale version of IOUT as described in paragraph 0022. In addition, these are normal design parameters/features in the field and the typical sense transistor would be smaller in size compared to the main one in order to reduce power consumption for the system, meeting claim 15.
Regarding claim 16, Ref~219 discloses the method according to claim 10, further comprising: coupling the sensing node to respective inputs of the second stage and the replica circuit as seen from Fig. 4, meeting claim 16.
Regarding claim 17, Ref~219 discloses the method according to claim 16, further comprising: detecting, via the clamp sense circuit (412 of Fig. 4), an output clamp condition of the second stage, the output clamp condition provided by a substantially fixed output voltage of the second stage for an increasing voltage (via ICLAMP of Fig. 4) at the sensing node, meeting claim 17.
Regarding claim 18, Ref~219 discloses the method according to claim 17, further comprising: configuring the replica circuit to output a decreasing voltage for the increasing voltage at the sensing node, since it is configured to operate in the same manner compared to the claimed one, meeting claim 18.
Regarding claim 19, Ref~219 discloses the method according to claim 17, further comprising: decoupling an output of the replica circuit from an output of the second stage, since it is configured in the same manner compared to the claimed one (please note the replica circuit and the second stage do NOT have a shared/common output), meeting claim 19.
Regarding claim 20, Ref~219 discloses the method according to claim 19, further comprising: coupling the output of the replica circuit to the current limiter as seen from Fig. 20, meeting claim 20.
Regarding claim 21, Ref~219 discloses the method according to claim 2, further comprising: coupling a feedback circuit (see VFB provided from a resistor dividerR1/R3 as seen from Fig. 4) between the output and an input (108 of Fig. 4) of the amplifier, meeting claim 21.
Regarding claim 22, Ref~219 discloses the method according to claim 2, further comprising: coupling a clamp circuit (412 of Fig. 4) to the output of the amplifier as seen; and
based on the coupling, clamping the output of the amplifier circuit (via ICLAMP of Fig. 4) when a non- compliant input is provided to the amplifier, meeting claim 22.
Regarding claim 23, Ref~219 supports the claimed “wherein: the non-compliant input is an input that is out of range with respect to an input voltage range of the amplifier”, since it is configured to operate in the same manner compared to the claimed one, meeting claim 23.
Regarding claim 24, Ref~219 discloses the method according to claim 22, wherein: the non-compliant input is an input that is out of range with respect to a linear region of operation of the amplifier, since it is configured to operate in the same manner compared to the claimed one and the clamping circuit is configured to detect an operating region of the output transistor and prevent the output transistor from exceeding a gate oxide tunneling voltage as advertised in paragraph [0005], meeting claim 24.
Allowable Subject Matter
Claims 6-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HIEU P NGUYEN whose telephone number is 571-272-8577. The examiner can normally be reached on Monday-Friday 8:30AM-6:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached on 571-272-5918. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/HIEU P NGUYEN/Primary Examiner, Art Unit 2843