DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 5-12, 14-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tada (U.S. PG Pub No US2016/0254276A1).
Regarding claim 1, Tada teaches a thin film transistor (TR) figs. 7-8 [0051], comprising:
a substrate (12) fig. 8 [0025];
a light-shielding layer (comprising G, LS1, LS2) fig. 8 [0051, 0034] (G forming GE1-2 formed of light shielding material [0029] like molybdenum [0029, 0034]) disposed on the substrate (12), comprising a first light-shielding pattern (G), a second light-shielding pattern (LS1) connected to the first light-shielding pattern (G), and a third light-shielding pattern (LS2) connected to the first light-shielding pattern (G) (G, LS1-2 commonly connected to TFT-TR power source [0023, 0053-0054]); and
an active layer (SC) fig. 8 [0027-0028] disposed on the light-shielding layer (comprising G, LS1, LS2), comprising a channel area (SCC1, LDD1, SCC2) fig. 8 [0028], a first conductive area (left LDD2, CSC) fig. 8 [0027] and a second conductive area (right LDD2, SCD) fig. 8 [0027] located on both sides (left/right sides) of the channel area (SCC1, LDD1, SCC2);
wherein an orthogonal projection of the first light-shielding pattern (GE 1-2) on the substrate (12) at least covers an orthogonal projection of the channel area (SCC1, LDD1, SCC2) on the substrate (12);
an orthographic projection of the second light-shielding pattern (LS1) on the substrate (12) overlaps at least a part of an orthographic projection of the first conductive area (left LDD2, CSC) on the substrate (12); and
an orthographic projection of the third light-shielding pattern (LS2) on the substrate (12) overlaps at least a part of an orthographic projection of the second conductive area (right LDD2, SCD) on the substrate (12) (see also fig. 7).
[AltContent: rect][AltContent: rect][AltContent: textbox (Z-shaped area in collective G, LS1, LS2 structure)][AltContent: arrow][AltContent: rect][AltContent: arrow][AltContent: arrow][AltContent: textbox (L-Shaped perimeters )][AltContent: rect][AltContent: rect][AltContent: rect][AltContent: rect]
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Annotated figs. 7-8 of Tada
Regarding claim 3, Tada teaches a thin film transistor (TR) figs. 7-8 [0051], comprising:
a substrate (12) fig. 8 [0025];
a light-shielding layer (comprising G, LS1, LS2) fig. 8 [0051, 0034] (G forming GE1-2 formed of light shielding material [0029] like molybdenum [0029, 0034]) disposed on the substrate (12), comprising a first light-shielding pattern (G), a second light-shielding pattern (LS1) connected to the first light-shielding pattern (G), and a third light-shielding pattern (LS2) connected to the first light-shielding pattern (G) (G, LS1-2 commonly connected to TFT-TR power source [0023, 0053-0054]);
an active layer (SC) fig. 8 [0027-0028] disposed on the light-shielding layer (comprising G, LS1, LS2), comprising a channel area (SCC1, LDD1, SCC2) fig. 8 [0028], a first conductive area (left LDD2, CSC) fig. 8 [0027] and a second conductive area (right LDD2, SCD) fig. 8 [0027] located on both sides (left/right sides) of the channel area (SCC1, LDD1, SCC2); and
a source (SE) fig. 8 [0027] and a drain (DE) fig. 8 [0027] disposed on the active layer (SC), connected to the first conductive area (left LDD2, CSC) and the second conductive area (right LDD2, SCD) respectively;
wherein an orthogonal projection of the first light-shielding pattern (GE 1-2) on the substrate (12) at least covers an orthogonal projection of the channel area (SCC1, LDD1, SCC2) on the substrate (12);
an orthographic projection of the second light-shielding pattern (LS1) on the substrate (12) overlaps at least a part of an orthographic projection of the first conductive area (left LDD2, CSC) on the substrate (12); and
an orthographic projection of the third light-shielding pattern (LS2) on the substrate (12) overlaps at least a part of an orthographic projection of the second conductive area (right LDD2, SCD) on the substrate (12) (see also fig. 7).
Regarding claim 5, Tada teaches the thin film transistor (TR) figs. 7-8 [0051] of claim 3. Tada also teaches wherein the light-shielding layer (comprising G, LS1, LS2) fig. 8 [0051, 0034] extends to an area (horizontally) corresponding to the source (SE) fig. 8 [0027] and the drain (DE) fig. 8 [0027].
Regarding claim 6, Tada teaches the thin film transistor (TR) figs. 7-8 [0051] of claim 5. Tada also teaches wherein the orthographic projections of the first conductive area (left LDD2, CSC) fig. 8 [0027] and the second conductive area (right LDD2, SCD) fig. 8 [0027] on the substrate (12) fig. 8 [0025] (partially) cover the orthographic projections of the second light-shielding pattern (LS1) fig. 8 [0051] and the third light-shielding pattern (LS2) fig. 8 [0051] on the substrate (12).
Regarding claim 7, Tada teaches the thin film transistor (TR) figs. 7-8 [0051] of claim 6. Tada also teaches wherein both the second light-shielding pattern (LS1) fig. 8 [0051] and the third light-shielding pattern (LS2) fig. 8 [0051] are L-shaped (have l-shaped perimeters), and the second light-shielding pattern (LS1) and the third light-shielding pattern (LS2) together form a right angle Z-shaped pattern (comprise Z-shaped area in collective light shielding layer structure, see annotated fig. 7 above).
Regarding claim 8, Tada teaches the thin film transistor (TR) figs. 7-8 [0051] of claim 5. Tada also teaches wherein the second light-shielding pattern (LS1) fig. 8 [0051] is disposed in a staggered manner (with horizontally-staggered arms) with the first conductive area (left LDD2, CSC) fig. 8 [0027] in an extension direction of the first conductive area (left LDD2, CSC), and the third light-shielding pattern (LS2) fig. 8 [0051] is disposed in a staggered manner (with horizontally-staggered arms) with the second conductive area (right LDD2, SCD) fig. 8 [0027] in an extension direction of the second conductive area (right LDD2, SCD); and
the orthographic projection of the first conductive area (left LDD2, CSC) on the substrate (12) fig. 8 [0025] does not fully cover the orthographic projection of the second light-shielding pattern (LS1) on the substrate (12); and,
the orthographic projection of the second conductive area (right LDD2, SCD) on the substrate (12) does not fully cover the orthographic projection of the third light-shielding pattern (LS2) on the substrate (12).
Regarding claim 9, Tada teaches the thin film transistor (TR) figs. 7-8 [0051] of claim 8. Tada also teaches wherein both the second light-shielding pattern (LS1) fig. 8 [0051] and the third light-shielding pattern (LS2) fig. 8 [0051] are L-shaped (have L-shaped perimeters), and the second light-shielding pattern (LS1) and the third light-shielding pattern (LS2) together form a multi-stepped pattern (with vertically-extending steps/arms).
Regarding claim 10, Tada teaches the thin film transistor (TR) figs. 7-8 [0051] of claim 3. Tada also teaches wherein the orthographic projection of the second light-shielding pattern (LS1) fig. 8 [0051] on the substrate (12) fig. 8 [0025] overlaps at least a part of an orthographic projection of the first conductive area (left LDD2, CSC) fig. 8 [0027] extending horizontally on the substrate (12), and the orthographic projection of the third light-shielding pattern (LS2) fig. 8 [0051] on the substrate (12) overlaps at least a part of an orthographic projection of the second conductive area (right LDD2, SCD) fig. 8 [0027] extending horizontally on the substrate (12).
Regarding claim 11, Tada teaches the thin film transistor (TR) figs. 7-8 [0051] of claim 10. Tada also teaches wherein the second light-shielding pattern (LS1) fig. 8 [0051] and the third light-shielding pattern (LS2) fig. 8 [0051] at least form one rectangular pattern (comprise rectangular areas; see annotated fig. 7 above).
Regarding claim 12, Tada teaches an array substrate (SUB1) fig. 8 [0025], wherein the array substrate comprises a thin film transistor (TR) figs. 7-8 [0051], and the thin film transistor comprises:
a substrate (12) fig. 8 [0025];
a light-shielding layer (comprising G, LS1, LS2) fig. 8 [0051, 0034] (G forming GE1-2 formed of light shielding material [0029] like molybdenum [0029, 0034]) disposed on the substrate (12), comprising a first light-shielding pattern (G), a second light-shielding pattern (LS1) connected to the first light-shielding pattern (G), and a third light-shielding pattern (LS2) connected to the first light-shielding pattern (G) (G, LS1-2 commonly connected to TFT-TR power source [0023, 0053-0054]);
an active layer (SC) fig. 8 [0027-0028] disposed on the light-shielding layer (comprising G, LS1, LS2), comprising a channel area (SCC1, LDD1, SCC2) fig. 8 [0028], a first conductive area (left LDD2, CSC) fig. 8 [0027] and a second conductive area (right LDD2, SCD) fig. 8 [0027] located on both sides (left/right sides) of the channel area (SCC1, LDD1, SCC2); and
a source (SE) fig. 8 [0027] and a drain (DE) fig. 8 [0027] disposed on the active layer (SC), connected to the first conductive area (left LDD2, CSC) and the second conductive area (right LDD2, SCD) respectively;
wherein an orthogonal projection of the first light-shielding pattern (GE 1-2) on the substrate (12) at least covers an orthogonal projection of the channel area (SCC1, LDD1, SCC2) on the substrate (12);
an orthographic projection of the second light-shielding pattern (LS1) on the substrate (12) overlaps at least a part of an orthographic projection of the first conductive area (left LDD2, CSC) on the substrate (12); and
an orthographic projection of the third light-shielding pattern (LS2) on the substrate (12) overlaps at least a part of an orthographic projection of the second conductive area (right LDD2, SCD) on the substrate (12) (see also fig. 7).
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Regarding claim 14, Tada teaches the array substrate (SUB1) fig. 8 [0025] of claim 12. Tada also teaches wherein the light-shielding layer (comprising G, LS1, LS2) fig. 8 [0051, 0034] extends to an area (horizontally) corresponding to the source (SE) fig. 8 [0027] and the drain (DE) fig. 8 [0027].
Regarding claim 15, Tada teaches the array substrate (SUB1) fig. 8 [0025] of claim 14. Tada also teaches wherein the orthographic projections of the first conductive area (left LDD2, CSC) fig. 8 [0027] and the second conductive area (right LDD2, SCD) fig. 8 [0027] on the substrate (12) fig. 8 [0025] (partially) cover the orthographic projections of the second light-shielding pattern (LS1) fig. 8 [0051] and the third light-shielding pattern (LS2) fig. 8 [0051] on the substrate (12).
Regarding claim 16, Tada teaches the array substrate (SUB1) fig. 8 [0025] of claim 15. Tada also teaches wherein both the second light-shielding pattern (LS1) fig. 8 [0051] and the third light-shielding pattern (LS2) fig. 8 [0051] are L-shaped (have l-shaped perimeters), and the second light-shielding pattern (LS1) and the third light-shielding pattern (LS2) together form a right angle Z-shaped pattern (comprise Z-shaped area in collective light shielding layer structure, see annotated fig. 7 above).
Regarding claim 17, Tada teaches the array substrate (SUB1) fig. 8 [0025] of claim 14. Tada also teaches wherein the second light-shielding pattern (LS1) fig. 8 [0051] is disposed in a staggered manner (with horizontally-staggered arms) with the first conductive area (left LDD2, CSC) fig. 8 [0027] in an extension direction of the first conductive area (left LDD2, CSC), and the third light-shielding pattern (LS2) fig. 8 [0051] is disposed in a staggered manner (with horizontally-staggered arms) with the second conductive area (right LDD2, SCD) fig. 8 [0027] in an extension direction of the second conductive area (right LDD2, SCD); and
the orthographic projection of the first conductive area (left LDD2, CSC) on the substrate (12) fig. 8 [0025] does not fully cover the orthographic projection of the second light-shielding pattern (LS1) on the substrate (12); and,
the orthographic projection of the second conductive area (right LDD2, SCD) on the substrate (12) does not fully cover the orthographic projection of the third light-shielding pattern (LS2) on the substrate (12).
Regarding claim 18, Tada teaches the array substrate (SUB1) fig. 8 [0025] of claim 17. Tada also teaches wherein both the second light-shielding pattern (LS1) fig. 8 [0051] and the third light-shielding pattern (LS2) fig. 8 [0051] are L-shaped (have L-shaped perimeters), and the second light-shielding pattern (LS1) and the third light-shielding pattern (LS2) together form a multi-stepped pattern (with vertically-extending steps/arms).
Regarding claim 19, Tada teaches the array substrate (SUB1) fig. 8 [0025] of claim 14. Tada also teaches wherein the orthographic projection of the second light-shielding pattern (LS1) fig. 8 [0051] on the substrate (12) fig. 8 [0025] overlaps at least a part of an orthographic projection of the first conductive area (left LDD2, CSC) fig. 8 [0027] extending horizontally on the substrate (12), and the orthographic projection of the third light-shielding pattern (LS2) fig. 8 [0051] on the substrate (12) overlaps at least a part of an orthographic projection of the second conductive area (right LDD2, SCD) fig. 8 [0027] extending horizontally on the substrate (12).
Regarding claim 20, Tada teaches the array substrate (SUB1) fig. 8 [0025] of claim 19. Tada also teaches wherein the second light-shielding pattern (LS1) fig. 8 [0051] and the third light-shielding pattern (LS2) fig. 8 [0051] at least form one rectangular pattern (comprise rectangular areas; see annotated fig. 7 above).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2, 4, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Tada (U.S. PG Pub No US2016/0254276A1), as applied in claims 1, 3, and 12 above, in view of Oh (U.S. PG Pub No US2017/0317155A1).
Regarding claim 2, Tada teaches the thin film transistor (TR) figs. 7-8 [0051] of claim 1. Tada also teaches wherein orthographic projections of the first conductive area (left LDD2, CSC) fig. 8 [0027] and the second conductive area (right LDD2, SCD) fig. 8 [0027] on the substrate (12) fig. 8 [0025] are both L-shaped (have L-shaped perimeters), the first conductive area (left LDD2, CSC) and the second conductive area (right LDD2, SCD) are connected through the channel area (SCC1, LDD1, SCC2) fig. 8 [0028].
However, Tada does not explicitly disclose an orthographic projection of the active layer (SC) fig. 8 [0027-0028] on the substrate (12) is right angle Z-shaped.
Oh teaches a semiconductor device [see fig. 3, 0059] comprising a thin film transistor (D-Tr) fig. 3 [0060] an orthographic projection of the active layer (165) fig. 3 [0060] on the substrate (100) fig. 4 [0064] is right angle Z-shaped [see fig. 3, 0070].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the shape of the active layer in the thin film transistor of Tada to be z-shaped [0070] in order to enhance its surface area for electrical connections in a limited space [0060] so as to improve the integration density of transistor circuitry [0060, 0070] while maintaining signal quality [0006-0008], as taught by Oh.
Regarding claim 4, Tada teaches the thin film transistor (TR) figs. 7-8 [0051] of claim 3. Tada also teaches wherein orthographic projections of the first conductive area (left LDD2, CSC) fig. 8 [0027] and the second conductive area (right LDD2, SCD) fig. 8 [0027] on the substrate (12) fig. 8 [0025] are both L-shaped (have L-shaped perimeters), the first conductive area (left LDD2, CSC) and the second conductive area (right LDD2, SCD) are connected through the channel area (SCC1, LDD1, SCC2) fig. 8 [0028].
However, Tada does not explicitly disclose an orthographic projection of the active layer (SC) fig. 8 [0027-0028] on the substrate (12) is right angle Z-shaped.
Oh teaches a semiconductor device [see fig. 3, 0059] comprising a thin film transistor (D-Tr) fig. 3 [0060] an orthographic projection of the active layer (165) fig. 3 [0060] on the substrate (100) fig. 4 [0064] is right angle Z-shaped [see fig. 3, 0070].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the shape of the active layer in the thin film transistor of Tada to be z-shaped [0070] in order to enhance its surface area for electrical connections in a limited space [0060] so as to improve the integration density of transistor circuitry [0060, 0070] while maintaining signal quality [0006-0008], as taught by Oh.
Regarding claim 13, Tada teaches the array substrate (SUB1) fig. 8 [0025] of claim 12. Tada also teaches wherein orthographic projections of the first conductive area (left LDD2, CSC) fig. 8 [0027] and the second conductive area (right LDD2, SCD) fig. 8 [0027] on the substrate (12) fig. 8 [0025] are both L-shaped (have L-shaped perimeters), the first conductive area (left LDD2, CSC) and the second conductive area (right LDD2, SCD) are connected through the channel area (SCC1, LDD1, SCC2) fig. 8 [0028].
However, Tada does not explicitly disclose an orthographic projection of the active layer (SC) fig. 8 [0027-0028] on the substrate (12) is right angle Z-shaped.
Oh teaches a semiconductor device [see fig. 3, 0059] comprising a thin film transistor (D-Tr) fig. 3 [0060] an orthographic projection of the active layer (165) fig. 3 [0060] on the substrate (100) fig. 4 [0064] is right angle Z-shaped [see fig. 3, 0070].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the shape of the active layer in the thin film transistor of Tada to be z-shaped [0070] in order to enhance its surface area for electrical connections in a limited space [0060] so as to improve the integration density of transistor circuitry [0060, 0070] while maintaining signal quality [0006-0008], as taught by Oh.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
All references made available on the PTO-892 form are considered relevant to the present disclosure because they all feature thin film transistors with light shielding elements.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEAN AYERS WINTERS whose telephone number is (571)270-3308. The examiner can normally be reached Monday - Friday 10:30 am - 7:00 pm (EST).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SEAN AYERS WINTERS/Examiner, Art Unit 2892 01/03/2026
/LEX H MALSAWMA/Primary Examiner, Art Unit 2892
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