DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
For the purpose of compact prosecution, multiple rejections are made with different references based on different interpretations, as well as to meet the limitations of dependent claims.
Claims 1-2, 6-8, 10-11, 15, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Green et al. (U.S. Patent No. 9,276,101).
Regarding to claim 1, Green teaches a semiconductor device, comprising:
a substrate (Fig. 23, element 50);
a first insulating film disposed on the substrate and having at least one via (Fig. 23, please see attached figure);
a second insulating film disposed on the first insulating film (Fig. 23, element 86);
a first adhesion layer disposed on the first insulating film (Fig. 23, element 82);
a first conductive structure disposed in the at least one via and having an extended portion extending to a top surface of the first insulating film (Fig. 23, element 78); and
a second adhesion layer disposed on the first conductive structure (Fig. 23, element 83), wherein the first adhesion layer covers at least a part of a bottom surface of the extended portion (Fig. 23, the first adhesion layer 82 covers at least a part of a bottom surface of the extended portion of conductive structure 78), and the second adhesion layer covers at least a part of a top surface of the first conductive structure (Fig. 23, the second adhesion layer 83 covers at least a part of a top surface of the first conductive structure 78).
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Regarding to claim 2, Green teaches the semiconductor device comprises a high electron mobility transistor (HEMT) (column 12, line 4).
Regarding to claim 6, Green teaches the first adhesion layer is disposed between the first insulating film and the second insulating film (Fig. 23).
Regarding to claim 7, Green teaches the second adhesion layer is disposed between the top surface of the first conductive structure and the second insulating film (Fig. 23, the second adhesion layer 83 is disposed between the top surface of the first conductive structure 78 and the second insulating film 86).
Regarding to claim 8, Green teaches the second adhesion layer covers a sidewall of the extended portion (Fig. 23).
Regarding to claim 10, Green teaches the first adhesion layer and the second adhesion layer are inorganic films (column 16, line 2, lines 25-25, Al2O3 and SiN are inorganic films).
Regarding to claim 11, Green teaches the first adhesion layer and the second adhesion layer comprise zirconium oxide (ZrO2), aluminum oxide (Al2O3), silicon dioxide (SiO2), silicon oxynitride (SiON), silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), aluminum nitride (AlN), titanium oxide (TiO2), hafnium oxide (HfO2), or tantalum oxide (Ta2O5) (column 16, line 2, lines 25-25).
Regarding to claim 15, Green teaches a semiconductor device, comprising:
a III-V compound semiconductor substrate (Fig. 23, element 50/51, column 8, lines 56-59);
a first insulating film disposed on the substrate and having at least one via (Fig. 23, please see attached figure);
a second insulating film disposed on the first insulating film (Fig. 23, element 86);
a first adhesion layer disposed on the first insulating film (Fig. 23, element 82);
a conductive structure disposed in the at least one via and on a top surface of the first insulating film (Fig. 23, element 78); and
a second adhesion layer disposed on the conductive structure (Fig. 23, element 83), wherein at least a part of the conductive structure is sandwiched between the first adhesion layer and the second adhesion layer (Fig. 23, part of the conductive structure 78 is sandwiched between first adhesion layer at this bottom and second adhesion layer on its top).
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Regarding to claim 20, Green teaches the first adhesion layer is disposed between the first insulating film and the second adhesion layer (Fig. 23).
Claims 1, 8-11, 14-15, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. (U.S. Patent No. 10,741,496).
Regarding to claim 1, Huang teaches a semiconductor device, comprising:
a substrate (Fig. 5, element 510);
a first insulating film disposed on the substrate and having at least one via (Fig. 5, element 530);
a second insulating film disposed on the first insulating film (Fig. 5, element 553);
a first adhesion layer disposed on the first insulating film (Fig. 5, element 555);
a first conductive structure disposed in the at least one via and having an extended portion extending to a top surface of the first insulating film (Fig. 5, element 560); and
a second adhesion layer disposed on the first conductive structure (Fig. 5, element 570), wherein the first adhesion layer covers at least a part of a bottom surface of the extended portion (Fig. 5, the first adhesion layer 555 covers at least a part of a bottom surface of the extended portion of conductive structure 560), and the second adhesion layer covers at least a part of a top surface of the first conductive structure (Fig. 5, the second adhesion layer 570 covers at least a part of a top surface of the first conductive structure 560).
Regarding to claim 8, Huang teaches the second adhesion layer covers a sidewall of the extended portion (Fig. 5, the second adhesion layer 570 covers a sidewall of the extended portion).
Regarding to claim 9, Huang teaches the first adhesion layer is in direct contact with the bottom surface of the extended portion, and the second adhesion layer is in direct contact with the top surface of the first conductive structure (Fig. 5, the first adhesion layer 555 is in direct contact with the bottom surface of the extended portion, and the second adhesion layer 570 is in direct contact with the top surface of the first conductive structure 560).
Regarding to claim 10, Huang teaches the first adhesion layer and the second adhesion layer are inorganic films (column 17, lines 17-20; column 10, lines 41-43).
Regarding to claim 11, Huang teaches the first adhesion layer and the second adhesion layer comprise zirconium oxide (ZrO2), aluminum oxide (Al2O3), silicon dioxide (SiO2), silicon oxynitride (SiON), silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), aluminum nitride (AlN), titanium oxide (TiO2), hafnium oxide (HfO2), or tantalum oxide (Ta2O5) (column 17, lines 17-20).
Regarding to claim 14, Huang teaches a second conductive structure disposed on the first conductive structure (Fig. 5, element 580).
Regarding to claim 15, Huang teaches a semiconductor device, comprising:
a III-V compound semiconductor substrate (Fig. 5, element 510, column 2, lines 57-60);
a first insulating film disposed on the substrate and having at least one via (Fig. 5, element 530);
a second insulating film disposed on the first insulating film (Fig. 5, element 553);
a first adhesion layer disposed on the first insulating film (Fig. 5, element 555);
a conductive structure disposed in the at least one via and on a top surface of the first insulating film (Fig. 5, element 560); and
a second adhesion layer disposed on the conductive structure (Fig. 5, element 570), wherein at least a part of the conductive structure is sandwiched between the first adhesion layer and the second adhesion layer (Fig. 5, part of the conductive structure 560 is sandwiched between first adhesion layer 555 at this bottom and second adhesion layer 570 on its top).
Regarding to claim 20, Huang teaches the first adhesion layer is disposed between the first insulating film and the second adhesion layer (Fig. 5, the first adhesion layer 555 is disposed between the first insulating film 530 and the second adhesion layer 570).
Claims 1, 8, 12, and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Anda et al. (U.S. Patent No. 6,051,454).
Regarding to claim 1, Anda teaches a semiconductor device, comprising:
a substrate (Fig. 4(c), element 21);
a first insulating film disposed on the substrate and having at least one via (Fig. 4(c), element 37);
a second insulating film disposed on the first insulating film (Fig. 4(c), element 21a);
a first adhesion layer disposed on the first insulating film (Fig. 4(c), element 35);
a first conductive structure disposed in the at least one via and having an extended portion extending to a top surface of the first insulating film (Fig. 4(c), element 38B); and
a second adhesion layer disposed on the first conductive structure (Fig. 4(c), element 36), wherein the first adhesion layer covers at least a part of a bottom surface of the extended portion (Fig. 4(c), the first adhesion layer 35 covers at least a part of a bottom surface of the extended portion of conductive structure 38B), and the second adhesion layer covers at least a part of a top surface of the first conductive structure (Fig. 4(c), the second adhesion layer 36 covers at least a part of a top surface of the first conductive structure 38).
Regarding to claim 8, Anda teaches the second adhesion layer covers a sidewall of the extended portion (Fig. 4(c)).
Regarding to claim 12, Anda teaches the first insulating film and the second insulating film are organic insulating films (column 8, lines 67-68; column 9, lines 19-20, photo resists are organic).
Regarding to claim 15, Anda teaches a semiconductor device, comprising:
a III-V compound semiconductor substrate (Fig. 4(c), element 21, column 8, lines 35-36);
a first insulating film disposed on the substrate and having at least one via (Fig. 4(c), element 37);
a second insulating film disposed on the first insulating film (Fig. 4(c), element 21a);
a first adhesion layer disposed on the first insulating film (Fig. 4(c), element 35);
a conductive structure disposed in the at least one via and on a top surface of the first insulating film (Fig. 4(c), element 38B); and
a second adhesion layer disposed on the conductive structure (Fig. 4(c), element 36), wherein at least a part of the conductive structure is sandwiched between the first adhesion layer and the second adhesion layer (Fig. 4(c), part of the conductive structure 38B is sandwiched between first adhesion layer 35 at this bottom and second adhesion layer 36 on its top).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (U.S. Patent No. 10,741,496), as applied to claim 1 above, in view of Lee (U.S. Patent No. 5,930,610).
Regarding to claim 3, Huang disclose the first conductive structure comprises a metal layer (column 18, line 2). Huang does not disclose a seed layer. Lee discloses a first conductive structure comprises a seed layer and a metal layer (Fig. 4, element 33, column 3, lines 39, conductive structure comprises a seed layer 33 and a metal layer 35). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Huang in view of Lee to comprise a seed layer in order to increase adhesion between the metal structure and the surrounding dielectrics.
Regarding to claim 4, Lee discloses the seed layer is disposed in the at least one via and covers sidewalls of the metal layer (Fig. 4).
Regarding to claim 5, Huang as modified results in the seed layer is disposed between the top surface of the first insulating film and a bottom surface of the metal layer (Fig. 5).
Claims 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (U.S. Patent No. 10,741,496), as applied to claim 15 above, in view of Lee (U.S. Patent No. 5,930,610).
Regarding to claim 16, Huang disclose the first conductive structure comprises a metal layer (column 18, line 2). Huang does not disclose a seed layer. Lee discloses a first conductive structure comprises a seed layer and a metal layer (Fig. 4, element 33, column 3, lines 39, conductive structure comprises a seed layer 33 and a metal layer 35). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Huang in view of Lee to comprise a seed layer in the first conductive structure in order to increase adhesion between the metal structure and the surrounding dielectrics.
Regarding to claim 17, Lee discloses a connected portion of the seed layer and a connected portion of the metal layer are disposed in the at least one via, and an extended portion of the seed layer and an extended portion of the metal layer are disposed on the top surface of the first insulating film (Fig. 4c).
Regarding to claim 18, Lee discloses the connected portion of the seed layer is disposed between the first insulating film and the connected portion of the metal layer (Fig. 4d).
Regarding to claim 19, Huang as modified results in the first adhesion layer is disposed between the first insulating film and the extended portion of the seed layer (Fig. 5).
Claim 13 are rejected under 35 U.S.C. 103 as being unpatentable over Anda et al. (U.S. Patent No. 6,051,454), as applied to claims 1 and 12 above, in view of LaRoche et al. (U.S. Patent Application Publication No. 2022/0140126).
Regarding to claim 13, Anda discloses the first insulating film and the second insulating film comprise photoresist (column 8, lines 67-68; column 9, lines 19-20). However, Anda does not specifically disclose the photoresist is benzocyclobutene (BCB). LaRoche discloses a photoresist is benzocyclobutene (BCB) ([0105], lines 29-30). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Anda in view of LaRoche to use BCB as photoresist in order to increase light sensitivity.
Pertinent Art
For the benefits of the Applicant, US-10566428-B2, US-7221015-B2, US-7750370-B2, and US-7468295-B2, are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. These references fail to disclose a second adhesion layer disposed on the first conductive structure, wherein the first adhesion layer covers at least a part of a bottom surface of the extended portion, the first adhesion layer and the second adhesion layer are inorganic films.
Conclusion
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/VU A VU/Primary Examiner, Art Unit 2897