Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed on 03/25/2026 have been fully considered but they are not persuasive.
The Applicant argues that in regard to claims 1 and 9 that the Sio prior art, does not teach the limitation of “a conductive plug continuously extending over the plurality of first conductive layers along the first direction, a bottom surface of the conductive plug being in contact with surfaces of the plurality of first conductive layers.”
In response to this argument, the Examiner directs the applicant’s attention to Sio prior art, which clearly teaches the limitation of a conductive plug (114 and 116) continuously extending over the plurality of first conductive layers (112) along the first direction, a bottom surface of the conductive plug (114 and 116) being in contact with surfaces of the plurality of first conductive layers (112) (see Sio, Fig.6B as shown below).
In addition, during patent examination, the pending claims must be "given their broadest reasonable interpretation consistent with the specification." In re Hyatt, 211 F.3d 1367, 1372, 54 USPQ2d 1664, 1667 (Fed. Cir. 2000). While the claims of issued patents are interpreted in light of the specification, prosecution history, prior art and other claims, this is not the mode of claim interpretation to be applied during examination. During examination, the claims must be interpreted as broadly as their terms reasonably allow. In re American Academy of Science Tech Center, F.3d, 2004 WL 1067528 (Fed. Cir. May 13, 2004) (The USPTO uses a different standard for construing claims than that used by district courts; during examination the USPTO must give claims their broadest reasonable interpretation.) This means that the words of the claim must be given their plain meaning unless applicant has provided a clear definition in the specification. In re Zletz, 893 F.2d 319, 321, 13 USPQ2d 1320, 1322 (Fed. Cir. 1989) >; Chef America, Inc. v. Lamb-Weston, Inc., 358 F.3d 1371, 1372, 69 USPQ2d 1857 (Fed. Cir. 2004).
The Examiner would further point out that “The use of patents as references is not limited to what the patentees describe as their own inventions or to the problems with which they are concerned. They are part of the literature of the art, relevant for all they contain.” In re Heck, 699 F.2d 1331, 1332-33, 216 USPQ 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (CCPA 1968)). Therefore, the Sio prior art reference does meet all the limitation in claims 1 and 9.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 6-12, 14-17, and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sio et al. (U.S. 2017/0117272 A1, hereinafter refer to Sio).
Regarding Claim 1: Sio discloses a semiconductor device (see Sio, Figs.6B and 10-13 as shown below and ¶ [0017]), comprising:
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a substrate (102) (see Sio, Fig.6B as shown above);
a plurality of first conductive layers (112) disposed over the substrate (102), the plurality of first conductive layers (112) being arranged in a first direction and each extending along a second direction perpendicular to the first direction (see Sio, Figs.6B and 10-13 as shown above);
a conductive plug (114 and 116) continuously extending over the plurality of first conductive layers (112) along the first direction, a bottom surface of the conductive plug (114 and 116) being in contact with surfaces of the plurality of first conductive layers (112) (see Sio, Fig.6B as shown above); and
a second conductive layer (118 and 120) disposed over the conductive plug (114 and 116), a bottom surface of the second conductive layer (118 and 120) being in contact with a top surface of the conductive plug (114 and 116) (see Sio, Fig.6B as shown above).
Regarding Claim 2: Sio discloses a semiconductor device as set forth in claim 1 as above. Sio further teaches wherein: the second conductive layer (118 and 120) extends in parallel to the conductive plug (114 and 116) (see Sio, Fig.6B as shown above).
Regarding Claim 3: Sio discloses a semiconductor device as set forth in claim 1 as above. Sio further teaches wherein an interlayer dielectric layer (208) disposed over the plurality of first conductive layers (112), the interlayer dielectric layer (208) having a through-hole (1106) therein, and the through-hole (1106) extends in the first direction and exposes top surfaces of the plurality of first conductive layers (112) at same time (see Sio, Figs.6B and 10-13 as shown above).
Regarding Claim 4: Sio discloses a semiconductor device as set forth in claim 3 as above. Sio further teaches wherein: the through-hole has a first size in the second direction, and the second conductive layer (118 and 120) has a second size in the second direction (see Sio, Figs.6B and 10-13 as shown above).
Regarding Claim 6: Sio discloses a semiconductor device as set forth in claim 3 as above. Sio further teaches wherein: a symmetry axis of the through-hole in the first direction overlaps with a symmetry axis of the second conductive layer (118 and 120) in the first direction (see Sio, Figs.6B and 10-13 as shown above).
Regarding Claim 7: Sio discloses a semiconductor device as set forth in claim 1 as above. Sio further teaches wherein: the conductive plug (114 and 116) is made of one or more combinations of tungsten, cobalt, copper, aluminum, and ruthenium (see Sio, Figs.6B and 10-13 as shown above and ¶ [0028]).
Regarding Claim 8: Sio discloses a semiconductor device as set forth in claim 3 as above. Sio further teaches wherein a barrier layer (504) disposed at a sidewall of the through-hole (1106), the conductive plug (114 and 116) being formed at a surface of the barrier layer (504) (see Sio, Figs.6B and 10-13 as shown above).
Regarding Claim 9: Sio discloses a method of forming a semiconductor device (see Sio, Figs.6B and 10-13 as shown above and ¶ [0017]), comprising:
providing a substrate (102) (see Sio, Fig.6B as shown above);
forming a plurality of first conductive layers (112) over the substrate (102), the plurality of first conductive layers (112) being arranged in a first direction and each extending along a second direction perpendicular to the first direction (see Sio, Fig.6B as shown above);
forming a conductive plug (114 and 116) continuously extending over the plurality of first conductive layers (112) along the first direction, a bottom surface of the conductive plug (114 and 116) being in contact with surfaces of the plurality of first conductive layers (112) (see Sio, Fig.6B as shown above); and
forming a second conductive layer (118 and 120) over the conductive plug (114 and 116), a bottom surface of the second conductive layer (118 and 120) being in contact with a top surface of the conductive plug (114 and 116) (see Sio, Fig.6B as shown above).
Regarding Claim 10: Sio discloses a method of forming a semiconductor device as set forth in claim 9 as above. Sio further teaches wherein: the second conductive layer (118 and 120) extends in parallel to the conductive plug (114 and 116) (see Sio, Fig.6B as shown above).
Regarding Claim 11: Sio discloses a method of forming a semiconductor device as set forth in claim 9 as above. Sio further teaches wherein before forming the conductive plug (114 and 116) over the plurality of first conductive layers (112) (see Sio, Figs.6B and 10-13 as shown above), further comprising:
forming an interlayer dielectric layer (208) over the plurality of first conductive layers (112) (see Sio, Figs.6B and 10-13 as shown above);
etching the interlayer dielectric layer (208) to form a through-hole (1106) in the interlayer dielectric layer (208), the through-hole (1106) extending in the first direction and exposing top surfaces of the plurality of first conductive layers (112) at the same time (see Sio, Figs.6B and 10-13 as shown above); and
forming the conductive plug (114 and 116) in the through-hole (1106) (see Sio, Figs.6B and 10-13 as shown above).
Regarding Claim 12: Sio discloses a method of forming a semiconductor device as set forth in claim 11 as above. Sio further teaches wherein: the through-hole (1106) has a first size in the second direction, and the second conductive layer (118 and 120) has a second size in the second direction (see Sio, Figs.6B and 10-13 as shown above).
Regarding Claim 14: Sio discloses a method of forming a semiconductor device as set forth in claim 11 as above. Sio further teaches wherein: a symmetry axis of the through-hole (1106) in the first direction overlaps with a symmetry axis of the second conductive layer (118 and 120) in the first direction (see Sio, Figs.6B and 10-13 as shown above).
Regarding Claim 15: Sio discloses a method of forming a semiconductor device as set forth in claim 9 as above. Sio further teaches wherein: the conductive plug (114 and 116) is made of a material comprising tungsten, cobalt, copper, aluminum, ruthenium, or a combination thereof (see Sio, Figs.6B and 10-13 as shown above and ¶ [0028]).
Regarding Claim 16: Sio discloses a method of forming a semiconductor device as set forth in claim 11 as above. Sio further teaches wherein forming a barrier layer (504) at a sidewall of the through-hole (1106), the conductive plug (114 and 116) being formed on a surface of the barrier layer (504) (see Sio, Figs.6B and 10-13 as shown above).
Regarding Claim 17: Sio discloses a method of forming a semiconductor device as set forth in claim 11 as above. Sio further teaches wherein forming the through-hole (1106) in the interlayer dielectric layer (208) includes: forming a graphic pattern layer (1104) on the interlayer dielectric layer (208), the graphic pattern layer (1104) having an opening pattern (see Sio, Figs.6B and 10-13 as shown above and ¶ [0059]);
using the graphic pattern layer (1104) as a mask to etch the interlayer dielectric layer (208) and form the through hole (1106) in the interlayer dielectric layer (208) (see Sio, Figs.6B and 10-13 as shown above and ¶ [0059]); and
removing the graphic pattern layer (1104) (see Sio, Figs.6B and 10-13 as shown above).
Regarding Claim 19: Sio discloses a method of forming a semiconductor device as set forth in claim 8 as above. Sio further teaches wherein the barrier layer (504) is made of TiN, or one or more combinations of Ti, TiN, TiO, Ta, and TaN (see Sio, Figs.6B and 10-13 as shown above and ¶ [0044]).
Regarding Claim 20: Sio discloses a method of forming a semiconductor device as set forth in claim 11 as above. Sio further teaches wherein forming the second conductive layer (118 and 120) (see Sio, Figs.6B and 10-13 as shown above) includes:
forming a dielectric layer (208c) on a surface of the interlayer dielectric layer (208a/208b) and a top surface of the conductive plug (114 and 116) (see Sio, Figs.15-16);
etching the dielectric layer (208c) to expose the top surface of the conductive plug (114 and 116) (see Sio, Figs.15-16);
forming a dielectric layer opening (1406/1506) in the dielectric layer (208c) (see Sio, Figs.15-16); and
filling in the dielectric layer opening (1406/1506) to form the second conductive layer (118 and 120) (see Sio, Figs.15-16).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Sio et al. (U.S. 2017/0117272 A1, hereinafter refer to Sio).
Regarding Claim 5: Sio discloses a semiconductor device as set forth in claim 4 as above. Sio is silent upon explicitly disclosing wherein: a ratio of the first size over the second size ranges from 50% to 80%.
However, Sio teaches wherein: the through-hole has a first size in the second direction, and the second conductive layer (118 and 120) has a second size in the second direction (see Sio, Figs.6B and 10-13 as shown above).
Hence, it would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the first size and the second size through routine experimentation and optimization to obtain optimal or desired device performance because the first size and the second size is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
Regarding Claim 13: Sio discloses a method of forming a semiconductor device as set forth in claim 12 as above. Sio is silent upon explicitly disclosing wherein: a ratio of the first size over the second size ranges from 50% to 80%.
However, Sio teaches wherein: the through-hole (1106) has a first size in the second direction, and the second conductive layer (116) has a second size in the second direction (see Sio, Figs.6B and 10-13 as shown above).
Hence, it would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the first size and the second size through routine experimentation and optimization to obtain optimal or desired device performance because the first size and the second size is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
Claim(s) 18 is rejected under 35 U.S.C. 103 as being unpatentable over Sio et al. (U.S. 2017/0117272 A1, hereinafter refer to Sio) as applied to claim 3 above, and further in view of LU (U.S. 2022/0115337 A1, hereinafter refer to LU).
Regarding Claim 18: Sio discloses a semiconductor device as applied to claim 3 above. Sio is silent upon explicitly disclosing wherein the interlayer dielectric layer is made of silicon nitride, silicon nitride boride, silicon oxynitride, or silicon oxynitride.
For support see LU, which teaches wherein the interlayer dielectric layer (404) is made of silicon nitride, silicon nitride boride, silicon oxynitride, or silicon oxynitride (see LU, ¶ [0097]).
Sio discloses the claimed invention except for material of interlayer dielectric layer. Thus, it would have been obvious to one having ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Sio and LU to enable the known silicon nitride material as alternative to silicon oxide material as taught by LU in order to form an interlayer dielectric layer, since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. In re Leshin, 125 USPQ 416.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BITEW A DINKE/Primary Examiner, Art Unit 2812
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