DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
CONTINUED EXAMINATION UNDER 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/6/2026 has been entered.
RESPONSE TO ARGUMENTS
Applicant’s arguments with respect to claims 1-2 and 4-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
I. REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Shonai et al. (US Patent 4,725,947) in view of Suzuki et al. (US Pub.: 2006/0253686) and Jin et al. (US Pub.: 2020/0117460).
As per claim 1, Shonai teaches/suggests a method comprising: to identify a block of code to fetch from a memory (e.g. associated with target instruction that would need to be properly identified for fetching from main memory for a first time: col. 1, l. 50 to col. 2, l. 11); causing the block of code to be fetched from a memory and loaded into a memory buffer (e.g. associated with fetching the target instruction from the main memory and storing the target instruction into associated memory for the first time: col. 1, l. 50 to col. 2, l. 11); receiving a request to supply processing circuitry with the block of code (e.g. associated with accessing the target instruction for a second time: col. 1, l. 50 to col. 2, l. 11); in response to determining that the block of code has already been loaded in the memory buffer (e.g. associated with accessing the target instruction for the second time, wherein the architecture would need to determine to know that the target instruction was already in the associated memory: col. 1, l. 50 to col. 2, l. 11), causing the block of code to be supplied to the processing circuitry (e.g. associated with the execution of the target instruction for the second time: col. 1, l. 50 to col. 2, l. 11) (col. 1, l. 6 to col. 2, l. 11).
Shonai does not teach the method comprising:
analyzing, by prefetch circuitry, branch logic in program code to prefetch accordingly;
responsive to determining that control circuitry is idle, having, by the prefetch circuitry, data prefetched by the control circuitry;
operating accordingly by prefetch circuitry; and
operating accordingly by prefetch circuitry.
Suzuki teaches/suggests a method comprising: analyzing, by prefetch circuitry, branch logic in program code to prefetch accordingly (e.g. associated with detecting branch target address register (S102) in order to prefetch branch target instruction (S103) in Fig. 2); having, by the prefetch circuitry, data prefetched (e.g. associated with prefetch branch target instruction (S103) in Fig. 2); operating accordingly by prefetch circuitry (e.g. associated with prefetch controller (13) operating); and operating accordingly by prefetch circuitry (e.g. associated with prefetch controller (13) operating) (Fig. 1-2; and [0045]-[0053]).
Jin teaches/suggests a method comprising: responsive to determining that control circuitry is idle, operating accordingly by the control circuitry ([0027])
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Suzuki and Jin’s prefetch operations into Shonai’s method for the benefit of allow the prefetching of the branch target instruction to be performed at an earlier timing (Suzuki, [0031]) and reducing the probability of delaying normal operations while improving bandwidth utilization (Jin, [0027]; and [0029]) to obtain the invention as specified in claim 1.
As per claim 2, Shonai, Suzuki and Jin teach/suggest all the claimed features of claim 1 above, where Shonai, Suzuki and Jin further teach/suggest the method further comprises, using the prefetch circuitry: receiving a different request to supply the processing circuitry with a different block of code; determining that the different block of code is not in the memory buffer; and causing the different block of code to be fetched from the memory and supplied to the processing circuitry (Shonai, col. 1, l. 50 to col. 2, l. 11; Suzuki, Fig. 1-2; [0045]-[0053]; and Jin, [0027]), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features for fetching another instruction that was not previously fetched.
As per claim 4, Shonai, Suzuki and Jin teach/suggest all the claimed features of claim 1 above, where Shonai, Suzuki and Jin further teach/suggest the method comprising wherein analyzing the branch logic in the program code to identify the block of code comprises analyzing branch logic in a preceding block of code already in the memory buffer, wherein the branch logic indicates a pathway through the program code that branches from the preceding block of code to the block of code (Shonai, col. 1, l. 50 to col. 2, l. 11; Suzuki, Fig. 1-2; Fig. 8A-8B; [0045]-[0055]; and Jin, [0027]), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 5, Shonai, Suzuki and Jin teach/suggest all the claimed features of claim 4 above, where Shonai, Suzuki and Jin further teach/suggest the method comprising wherein the program code comprises pages of code, each divided into bursts, wherein the block of code comprises one burst of the code, wherein the preceding block of code comprises one or more other bursts of the code that, in an order of execution of the program code, precede the block of code (Shonai, col. 1, l. 50 to col. 2, l. 11; Suzuki, Fig. 1-2; Fig. 8A-8B; [0045]-[0055]; and Jin, [0027]; [0049]-[0050]), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 6, Shonai, Suzuki and Jin teach/suggest all the claimed features of claim 5 above, where Shonai, Suzuki and Jin further teach/suggest the method comprising wherein causing the block of code to be prefetched from the memory and loaded into a memory buffer occurs in response to a request to supply the processing circuitry with the preceding block of code, and wherein the memory comprises flash memory (Shonai, col. 1, l. 50 to col. 2, l. 11; Suzuki, Fig. 1-2; Fig. 8A-8B; [0045]-[0055]; and Jin, [0016]-[0017]; [0027]; [0049]-[0050]), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Shonai et al. (US Patent 4,725,947) in view of Suzuki et al. (US Pub.: 2006/0253686) and Jin et al. (US Pub.: 2020/0117460) as applied to claim 1 above, and further in view of Johnson et al. (US Pub.: 2005/0015664).
As per claim 7, Shonai, Suzuki and Jin teach/suggest all the claimed features of claim 1 above, but Shonai, Suzuki and Jin do not teach the method further comprising, using the prefetch circuitry, detecting a fault in the block of code, and in response, alerting the processing circuitry to the fault.
Johnson teach/suggest a method comprising using the prefetch circuitry, detecting a fault in the block of code (e.g. associated with detecting uncorrectable error: [0052]), and in response, alerting the processing circuitry to the fault (e.g. associated with sending an interrupt signal to CPU/requester for error recover process: [0055]-[0056]) (Fig. 1-3; Fig. 8; [0047]-[0059]; [0066]; and [0087]-[0093]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Johnson’s error detection into Shonai, Suzuki and Jin’s method for the benefit properly identifying uncorrectable errors in prefetched data and carrying out error recovery without needlessly incurring overhead (Johnson, [0092]) to obtain the invention as specified in claim 7.
As per claim 8, Shonai, Suzuki, Jin and Johnson teach/suggest all the claimed features of claim 7 above, where Shonai, Suzuki, Jin and Johnson further teach/suggest the method further comprising the processing circuitry, in response to being alerted to the fault, directing the prefetch circuitry to verify the fault (Shonai, col. 1, l. 50 to col. 2, l. 11; Suzuki, Fig. 1-2; [0045]-[0053]; Jin, [0016]-[0017]; [0027]; [0049]-[0050]; and Johnson, Fig. 1-3; Fig. 8; [0047]-[0059]; [0087]-[0093]), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features as the fault is corrected.
Claims 9-12 are rejected under 35 U.S.C. 103 as being unpatentable over Shonai et al. (US Patent 4,725,947) in view of Suzuki et al. (US Pub.: 2006/0253686) and Bailey (US Pub.: 2004/0042278).
As per claim 9, Shonai teaches/suggests a system comprising: processing circuitry configurable to execute program code (e.g. associated with processor executing instruction: col. 1, l. 6 to col. 2, l. 11); and to identify a block of code to fetch from a memory (e.g. associated with target instruction that would need to be properly identified for fetching from main memory for a first time: col. 1, l. 50 to col. 2, l. 11); cause the block of code to be fetched from the memory and loaded into a memory buffer (e.g. associated with fetching the target instruction from the main memory and storing the target instruction into associated memory for the first time: col. 1, l. 50 to col. 2, l. 11); receive a request to supply the processing circuitry with the block of code; determine that the block of code is already in the memory buffer (e.g. associated with accessing the target instruction for a second time: col. 1, l. 50 to col. 2, l. 11); and cause the block of code to be supplied to the processing circuitry (e.g. associated with the execution of the target instruction for the second time: col. 1, l. 50 to col. 2, l. 11) (col. 1, l. 6 to col. 2, l. 11).
Shonai does not teach the system comprising:
prefetch circuitry coupled to the processing circuitry and configurable to:
analyze branch logic in the program code to prefetch accordingly, wherein the block of code comprises multiple bursts of code;
data to be prefetched.
Suzuki teaches/suggests a system comprising: prefetch circuitry coupled to the processing circuitry (Fig. 1) and configurable to: analyze branch logic in the program code to prefetch accordingly, wherein the block of code comprises code (e.g. associated with detecting branch target address register (S102) in order to prefetch branch target instruction (S103) in Fig. 2); and data to be prefetched (e.g. associated with prefetch branch target instruction (S103) in Fig. 2) (Fig. 1-2; and [0045]-[0053]).
Bailey teaches/suggests a system comprising: comprises multiple bursts of data ([0011]-[0013])
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Suzuki’s prefetch operations and Bailey’s data bursts into Shonai’s system for the benefit of allow the prefetching of the branch target instruction to be performed at an earlier timing (Suzuki, [0031]) and increasing the bandwidth of data transfer (Bailey, [0010]) to obtain the invention as specified in claim 9.
As per claim 10, Shonai, Suzuki and Bailey teach/suggest all the claimed features of claim 9 above, where Shonai, Suzuki and Bailey further teach/suggest the system comprising wherein the prefetch circuitry is further configured to: receive a different request to supply the processing circuitry with a different block of code; determine that the different block of code is not in the memory buffer; and cause the different block of code to be fetched from the memory and supplied to the processing circuitry (Shonai, col. 1, l. 50 to col. 2, l. 11; Suzuki, Fig. 1-2; [0045]-[0053]; and Bailey, [0011]-[0013]), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features for fetching another instruction that was not previously fetched.
As per claim 11, Shonai, Suzuki and Bailey teach/suggest all the claimed features of claim 9 above, where Shonai, Suzuki and Bailey further teach/suggest the system comprising wherein, to analyze the branch logic in the program code to identify the block of code, the prefetch circuitry is configured to analyze branch logic in a preceding block of code already in the memory buffer, wherein the branch logic indicates a pathway through the program code that branches from the preceding block of code to the block of code (Shonai, col. 1, l. 50 to col. 2, l. 11; Suzuki, Fig. 1-2; Fig. 8A-8B; [0045]-[0055]; and Bailey, [0011]-[0013]), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 12, Shonai, Suzuki and Bailey teach/suggest all the claimed features of claim 11 above, where Shonai, Suzuki and Bailey further teach/suggest the system comprising wherein the program code comprises pages of code, each divided into bursts, wherein the block of code comprises one burst of the code, and wherein the preceding block of code comprises one or more other bursts of the code that, in an order of execution of the program code, precede the block of code (Shonai, col. 1, l. 50 to col. 2, l. 11; Suzuki, Fig. 1-2; Fig. 8A-8B; [0045]-[0055]; and Bailey, [0011]-[0013]), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features.
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Shonai et al. (US Patent 4,725,947) in view of Suzuki et al. (US Pub.: 2006/0253686) and Bailey (US Pub.: 2004/0042278) as applied to claims 12 and 9, and further in view of Jin et al. (US Pub.: 2020/0117460).
As per claims 13-14, Shonai, Suzuki and Bailey teach/suggest all the claimed features of claims 9 and 12 above, where Shonai, Suzuki and Bailey further teach/suggest the system comprising: wherein the prefetch circuitry causes the block of code to be prefetched from the memory and loaded into the memory buffer in response to the processing circuitry requesting the preceding block of code (Shonai, col. 1, l. 50 to col. 2, l. 11; Suzuki, Fig. 1-2; Fig. 8A-8B; [0045]-[0055]; and Bailey, [0011]-[0013]).
Shonai, Suzuki and Bailey do not teach the system comprising:
wherein the memory comprises flash memory; and
wherein the prefetch circuitry is further configured to monitor for when flash control circuitry associated with the memory is idle, and wherein the prefetch circuitry causes the block of code to be prefetched from the memory only when the flash control circuitry is idle.
Jin teach/suggest a system comprising: wherein the memory comprises flash memory; and wherein the prefetch circuitry is further configured to monitor for when flash control circuitry associated with the memory is idle, and wherein the prefetch circuitry causes the block of code to be prefetched from the memory only when the flash control circuitry is idle ([0016]-[0017]; and [0027])
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Jin’s prefetch operations into Shonai, Suzuki and Bailey’s system for the benefit of reducing the probability of delaying normal operations while improving bandwidth utilization (Jin, [0027]; and [0029]) to obtain the invention as specified in claims 13-14.
Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Shonai et al. (US Patent 4,725,947) in view of Suzuki et al. (US Pub.: 2006/0253686) and Bailey (US Pub.: 2004/0042278) as applied to claim 9 above, and further in view of Johnson et al. (US Pub.: 2005/0015664).
As per claim 15, Shonai, Suzuki and Bailey teach/suggest all the claimed features of claim 9 above, but Shonai, Suzuki and Bailey do not teach the system comprising wherein the prefetch circuitry is further configurable to detect a fault in the block of code requested by the processing circuitry, and in response, alert the processing circuitry to the fault.
Johnson teach/suggest a system comprising wherein the prefetch circuitry is further configurable to detect a fault in the block of code requested by the processing circuitry (e.g. associated with detecting uncorrectable error: [0047]; [0052]), and in response, alert the processing circuitry to the fault (e.g. associated with sending an interrupt signal to CPU/requester for error recover process: [0055]-[0056]) (Fig. 1-3; Fig. 8; [0047]-[0059]; [0066]; and [0087]-[0093])
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Johnson’s error detection into Shonai, Suzuki and Bailey’s method for the benefit properly identifying uncorrectable errors in prefetched data and carrying out error recovery without needlessly incurring overhead (Johnson, [0092]) to obtain the invention as specified in claim 15.
As per claim 16, Shonai, Suzuki, Bailey and Johnson teach/suggest all the claimed features of claim 15 above, where Shonai, Suzuki, Bailey and Johnson further teach/suggest the system comprising wherein the processing circuitry is further configurable to, in response to being alerted to the fault, direct the prefetch circuitry to verify the fault (Shonai, col. 1, l. 50 to col. 2, l. 11; Suzuki, Fig. 1-2; [0045]-[0053]; Bailey, [0011]-[0013]; and Johnson, Fig. 1-3; Fig. 8; [0047]-[0059]; [0087]-[0093]), wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features as the fault is corrected.
Claims 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Shonai et al. (US Patent 4,725,947) in view of Suzuki et al. (US Pub.: 2006/0253686) and Johnson et al. (US Pub.: 2005/0015664).
As per claim 17, Shonai teaches/suggests a circuit comprising: to identify a block of code (e.g. associated with target instruction that would need to be properly identified for fetching from main memory for a first time: col. 1, l. 50 to col. 2, l. 11); and cause the block of code to be fetched from memory and loaded into a memory buffer (e.g. associated with fetching the target instruction from the main memory and storing the target instruction into associated memory for the first time: col. 1, l. 50 to col. 2, l. 11); receive a request by processing circuitry for the block of code (e.g. associated with accessing the target instruction for a second time: col. 1, l. 50 to col. 2, l. 11); cause the block of code to be supplied to the processing circuitry; and operate with the block of code; operate with the block of code (e.g. associated with the execution of the target instruction for the second time: col. 1, l. 50 to col. 2, l. 11) (col. 1, l. 6 to col. 2, l. 11).
Shonai does not teach the circuit comprising:
prefetch control circuitry;
branch prediction circuitry configurable to analyze branch logic in program code; and
fault prediction circuitry;
wherein the prefetch control circuitry is configurable to:
have data prefetched; and
instruct the fault prediction circuitry to detect whether there is a fault in data;
wherein the fault prediction circuitry is configurable to:
detect whether there is a fault in data; and
responsive to detecting the fault, alert the prefetch control circuitry of the fault; and
wherein the prefetch control circuitry is further configurable to, responsive to receiving an alert of the fault, alert the processing circuitry to the fault.
Suzuki teaches/suggests a circuit comprising: prefetch control circuitry; branch prediction circuitry configurable to analyze branch logic in program code (e.g. associated with detecting branch target address register (S102) in order to prefetch branch target instruction (S103) in Fig. 2); wherein the prefetch control circuitry is configurable to: have data prefetched (e.g. associated with prefetch branch target instruction (S103) in Fig. 2) (Fig. 1-2; and [0045]-[0053]).
Johnson teaches/suggests a circuit comprising: fault prediction circuitry (Fig. 2, ref. 204); instruct the fault prediction circuitry to detect whether there is a fault in data (e.g. associated with detecting uncorrectable error: [0052]); wherein the fault prediction circuitry is configurable to: detect whether there is a fault in data (e.g. associated with detecting uncorrectable error in prefetched data: [0052]); and responsive to detecting the fault, alert the prefetch control circuitry of the fault (e.g. associated with storing of an identifier for the detected prefetched data with uncorrectable error: [0053]; [0066]); and wherein the prefetch control circuitry is further configurable to, responsive to receiving an alert of the fault, alert the processing circuitry to the fault (e.g. associated with sending an interrupt signal to CPU/requester for error recover process: [0055]-[0056]) (Fig. 1-3; Fig. 8; [0047]-[0059]; [0066]; and [0087]-[0093]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Suzuki’s prefetching and Johnson’s error detection into Shonai’s circuit for the benefit of allow the prefetching of the branch target instruction to be performed at an earlier timing (Suzuki, [0031]) and properly identifying uncorrectable errors in prefetched data and carrying out error recovery without needlessly incurring overhead (Johnson, [0092]) to obtain the invention as specified in claim 17.
As per claim 18, Shonai, Suzuki and Johnson teach/suggest all the claimed features of claim 17 above, where Shonai, Suzuki and Johnson further teach/suggest the circuit comprising wherein, to analyze the branch logic in the program code to identify the block of code, the branch prediction circuitry is configured to analyze branch logic in a preceding block of code already in the memory buffer, wherein the branch logic indicates a pathway through the code that branches from the preceding block of code to the block of code (Shonai, col. 1, l. 50 to col. 2, l. 11; Suzuki, Fig. 1-2; Fig. 8A-8B; [0045]-[0055]; and Johnson, Fig. 1-3; Fig. 8; [0047]-[0059]; [0066]; [0087]-[0093]) wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features.
As per claim 19, Shonai, Suzuki and Johnson teach/suggest all the claimed features of claim 18 above, where Shonai, Suzuki and Johnson further teach/suggest the circuit comprising wherein the code comprises pages of code, each divided into bursts, wherein the block of code comprises one burst of the code, and wherein the preceding block of code comprises one or more other bursts of the code that, in an order of execution of the program code, precede the block of code (Shonai, col. 1, l. 50 to col. 2, l. 11; Suzuki, Fig. 1-2; Fig. 8A-8B; [0045]-[0055]; and Johnson, Fig. 1-3; Fig. 8; [0047]-[0059]; [0066]; [0087]-[0093]) wherein it would have been obvious to one of ordinary skilled in the art to further implement the above claimed features.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Shonai et al. (US Patent 4,725,947) in view of Suzuki et al. (US Pub.: 2006/0253686) and Johnson et al. (US Pub.: 2005/0015664) as applied to claim 19, and further in view of Jin et al. (US Pub.: 2020/0117460).
As per claim 20, Shonai, Suzuki and Johnson teach/suggest all the claimed features of claim 19 above, where Shonai, Suzuki and Johnson further teach/suggest the circuit comprising wherein the prefetch control circuitry causes the block of code to be prefetched from the memory and loaded into a memory buffer in response to the processing circuitry requesting the preceding block of code (Shonai, col. 1, l. 50 to col. 2, l. 11; Suzuki, Fig. 1-2; Fig. 8A-8B; [0045]-[0055]; and Johnson, Fig. 1-3; Fig. 8; [0047]-[0059]; [0066]; [0087]-[0093]), but Shonai, Suzuki and Johnson do not expressly teach the circuit comprising wherein the memory comprises flash memory
Jin teach/suggest a circuit comprising: wherein the memory comprises flash memory ([0016]-[0017])
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Jin’s prefetch operations into Shonai, Suzuki and Johnson’s system for the benefit of reducing the probability of delaying normal operations while improving bandwidth utilization (Jin, [0027]; and [0029]) to obtain the invention as specified in claim 20.
III. CLOSING COMMENTS
CONCLUSION
STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-2 and 4-20 have received a first action on the merits and are subject of a first action non-final.
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHUN KUAN LEE whose telephone number is (571)272-0671. The examiner can normally be reached Monday-Friday.
IMPORTANT NOTE
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached on (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHUN KUAN LEE/Primary Examiner
Art Unit 2181 July 17, 2026
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