DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 7, 15, 17, & 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Borowiec (US Patent 5,170,337) in view of Korman (USPatent5,043,859) in view of Lenniger (US Pub no. 2013/0134572 A1)
Regarding claim 1, Borowiec et al discloses A transistor package comprising:
a substrate(20’); a transistor(Q1) in thermal contact with the substrate(20’) (col. 3, lines 52-60); and a Kelvin connection, the Kelvin connection (G1’)having a first connector directly coupled at a first end to a transistor gate (10)of the transistor (Q1)and a second connector(Sk1’) directly coupled at a first end to a differing terminal(source terminal 12) of the transistor(Col. 4, lines 13-17).
Borowiec et al fails to teach the substrate directly sintered to a heat sink through a sintered layer, wherein the heat sink comprise fins; an encapsulant that at least partially encapsulates the transistor, wherein the encapsulant further encapsulates a portion of each of the first connector and the second connector, including the first end of the first connector and the first end of the second connector.
Korman et al teaches an encapsulant that at least partially encapsulates the transistor (MOSFET), wherein the encapsulant further encapsulates a portion of each of the first connector (166)and the second connector(164), including the first end of the first connector and the first end of the second connector (col. 6 lines 39-51;col. 8, lines 5-19). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify , Borowiec et al with the teachings of Korman et al to provide a packaged device.
Borowiec et al in view of Korman et al discloses the limitations above but fails to teach the substrate directly sintered to a heat sink through a sintered layer, wherein the heat sink comprise fins.
Lenniger et al discloses a substrate (132a or 132b)directly sintered to a heat sink(104) through a sintered layer(118), wherein the heat sink comprise fins(112) [0030-0031]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further modify Borowiec et al & Korman et al with the teachings of Lenniger et al to prevent overheating.
Regarding claim 7, Borowiec et al in view of Korman et al in view of Lenniger et al discloses all the claim limitations of claim 1 but fails to teach wherein the transistor comprises a gallium nitride.
However, in the background of the invention, Lenniger et al wherein the transistor comprises a gallium nitride [0002]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Borowiec et al & Korman et al with the teachings of Lenniger et al to provide suitable materials to produce power electronic modules.
Regarding claim 15, Borowiec et al discloses An inverter comprising: wherein each of the transistor packages includes: a transistor (Q1); a transistor(Q1) in thermal contact with the substrate(20’) (col. 3, lines 52-60); and a Kelvin connection, the Kelvin connection (G1’)having a first connector directly coupled at a first end to a transistor gate (10)of the transistor (Q1)and a second connector(Sk1’) directly coupled at a first end to a differing terminal(source terminal 12) of the transistor(Col. 4, lines 13-17).
Borowiec et al fails to teach a housing, wherein the housing is formed of a metal and is a heat sink, the housing configured to house a plurality of transistor packages wherein the heat sink comprises fins; wherein the transistor substrate is directly sintered to
the housing through a sintered layer; an encapsulant that at least partially encapsulates the transistor; and wherein the encapsulant further encapsulates a portion of each of the first connector and the second connector, including the first end of the first connector and the first end of the second connector.
However, Korman et al teaches a housing(copper frame ), wherein the housing is formed of a metal and is a heat sink, the housing configured to house a plurality of transistor(Q1-Q4) packages (col. 8, lines 15-20); an encapsulant that at least partially encapsulates the transistor (MOSFET), wherein the encapsulant further encapsulates a portion of each of the first connector (166)and the second connector(164), including the first end of the first connector and the first end of the second connector (col. 6 lines 39-51;col. 8, lines 5-19). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify , Borowiec et al with the teachings of Korman et al to provide a packaged device.
Borowiec et al in view of Korman et al discloses the limitations above but fails to teach wherein the transistor substrate is directly sintered to the housing through a sintered layer.
However, Lenniger et al discloses a substrate sintered (132)to a heat sink (104)through a sintered layer(118), the heat sink comprising fins (112)[0029-0031]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further modify Borowiec et al & Korman et al with the teachings of Lenniger et al to prevent overheating
Regarding claim 17, Korman et al wherein the transistor is an insulated-gate bipolar transistor(col. 8, lines 34-35) Lenniger et al discloses comprising gallium nitride [0002].
Regarding claim 19, Lenniger et al discloses wherein the sintered layer (118)comprises silver[0047]
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Borowiec (US Patent 5,170,337) in view of Lenniger (US Pub no. 2013/0134572 A1)
Regarding claim 8, Borowiec et al discloses A transistor package (Fig. 2) comprising: a transistor (Q1)in thermal contact with a substrate(20’) (col. 3, lines 52-60); and a Kelvin connection, the Kelvin connection having a first connector(G1’) directly coupled at a first end to a transistor gate (10)of the transistor (Q1)and a second connector (Sk1’)directly coupled at a first end to a differing terminal of the transistor (source terminal 12)(Col. 4, lines 13-17).
Borowiec et al fails to teach the substrate directly sintered to a heat sink through a sintered layer.
Lenniger et al discloses a substrate (132a or 132b)directly sintered to a heat sink(104) through a sintered layer(118) [0030-0031]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Borowiec et al with the teachings of Lenniger et al to prevent overheating.
Regarding claim 13, Borowiec et al in view of Lenniger et al discloses all the claim limitations of claim 8 but fails to teach wherein the transistor comprises a gallium nitride
However, in the background of the invention, Lenniger et al wherein the transistor comprises a gallium nitride [0002]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Borowiec et al with the teachings of Lenniger et al to provide suitable materials to produce power electronic modules.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Borowiec (US Patent 5,170,337) in view of Lenniger (US Pub no. 2013/0134572 A1) as applied to claim 8 and further in view of Korman (USPatent5,043,859).
Regarding claim 10, Borowiec et al as modified by Lenniger et al discloses all the claim limitations of claim 8 but fails to teach further comprising an encapsulant that at least partially encapsulates the transistor, and wherein the encapsulant further encapsulates a portion of each of the first connector and the second connector, including the first end of the first connector and the first end of the second connector.
However, Korman et al teaches an encapsulant that at least partially encapsulates the transistor (MOSFET), wherein the encapsulant further encapsulates a portion of each of the first connector (166)and the second connector(164), including the first end of the first connector and the first end of the second connector (col. 6 lines 39-51;col. 8, lines 5-19). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify , Borowiec et al & Lenniger et al with the teachings of Korman et al to provide a packaged device.
Claim(s) 11 & 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Borowiec (US Patent 5,170,337) in view of Lenniger (US Pub no. 2013/0134572 A1) as applied to claim 8 and further in view of Pavier (US Pub no. 2002/00967748 A1).
Regarding claim 11, Borowiec et al as modified by Lenniger et al discloses all the claim limitations of claim 8 but fails to teach further comprising a diode structure that is in series with the transistor.
However, Pavier et al discloses switching device comprising an IGBT die and a series connected diode[0029]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further modify the teachings of Borowiec et al & Lenniger et al with the teachings of Pavier et al to provide control of the power die.
Regarding claim 12, Pavier et al discloses wherein the transistor is an insulated-
gate bipolar transistor [0029].
Claim(s) 4-6 & 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Borowiec (US Patent 5,170,337) in view of Korman (USPatent5,043,859) and Lenniger (US Pub no. 2013/0134572 A1)as applied to claim 1 & 17 and further in view of Pavier (US Pub no. 2002/00967748 A1).
Regarding claim 4, Borowiec et al as modified by Korman et al and Lenniger et al discloses all the claim limitations of claim 1 but fails to teach , further comprising a diode structure that is in series with the transistor.
However, Pavier et al discloses switching device comprising an IGBT die and a series connected diode[0029]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further modify the teachings of Borowiec et al ,Korman et al and Lenniger et al with the teachings of Pavier et al to provide control of the power die.
Regarding claim 5, Pavier et al discloses wherein the transistor is an insulated-
gate bipolar transistor[0029].
Regarding claim 6, Borowiec et al discloses wherein the transistor is a metal-oxide-
semiconductor-field-effect transistor(Col. 4, lines 13-17)..
Regarding claim 18, Borowiec et al as modified by Korman et al and Lenniger et al discloses all the claim limitations of claim 17 but fails to teach further comprising a diode structure that is in series with the transistor.
However, Pavier et al discloses switching device comprising an IGBT die and a series connected diode[0029]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further modify the teachings of Borowiec et al ,Korman et al and Lenniger et al with the teachings of Pavier et al to provide control of the power die.
Claims 3 & 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Borowiec (US Patent 5,170,337) in view of Korman (USPatent5,043,859) in view Lenniger (US Pub no. 2013/0134572 A1) as applied to claim 1 and 15 and further in view of Ikeda (US Pub no. 2017/0311482 A1).
Regarding claim 3, Borowiec as modified by Korman ,Lenniger et al discloses all the claim limitations of claim 1 but fails to teach wherein the heat sink
comprises contact pads.
However, Ikeda et al discloses a heat dissipating structure wherein a heat sink
(51)comprises contact pads (50) [0063] fig. 6a. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further modify Borowiec et al , Korman & Lenniger et al with the teachings of Ikeda et al to reduce electrical resistance.
Regarding claim 20, Borowiec as modified by Korman ,Lenniger et al discloses all the claim limitations of claim 15 but fails to teach wherein the heat sink
comprises contact pads.
However, Ikeda et al discloses a heat dissipating structure wherein a heat sink
(51)comprises contact pads (50) [0063] fig. 6a. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further modify Borowiec et al , Korman & Lenniger et al with the teachings of Ikeda et al to reduce electrical resistance.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1,3-8,13,15,17-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Conclusion
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/LATANYA N CRAWFORD EASON/Primary Examiner, Art Unit 2813
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