DETAILED ACTION
This Office Action is in response to Applicant’s application 18/498,559 filed on October 31, 2023 in which claims 1 to 25 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings submitted on October 31, 2023 have been reviewed and accepted by the Examiner.
Notation
References to patents will be in the form of [C:L] where C is the column number and L is the line number. References to pre-grant patent publications will be to the paragraph number in the form of [xxxx].
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
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Claims 1-2, 5-6 and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. 2017/0373189 (Lee).
Regarding claim 1 and referring to annotated Figures 8 and 10A, Lee discloses a semiconductor device, comprising:
a first p-channel field effect transistor (p-FET), as annotated and described at [0035], including:
a first gate dielectric layer, 222 [0021] as annotated, on a surface of a substrate, as shown;
a first gate structure, 224 [0030], on the first gate dielectric layer, as shown; and
first silicon-germanium (SiGe) regions, 242a [0031, 35], disposed in the substrate, as shown, on both sides of the first gate structure, as shown, the first SiGe regions extended to a first depth, D1 [0031], from the surface of the substrate, as shown; and
a second p-FET including, as annotated and described at [0035]:
a second gate dielectric layer, 222 [0021], on the surface of the substrate, as shown;
a second gate structure, 224 [0030], on the second gate dielectric layer, as shown; and
second SiGe regions, 242b [0031, 35] disposed in the substrate, as shown, on both sides of the second gate structure, as shown, the second SiGe regions extended to a second depth from the surface of the substrate, D2 as shown, the second depth different than the first depth, as described at [0031] and shown.
Regarding claim 2 which depends upon claim 1, wherein Lee teaches the first SiGe regions are laterally spaced away from respective sidewalls of the first gate structure by a first distance, X1 [0032]; and the second SiGe regions are laterally spaced away from respective sidewalls of the second gate structure by a second distance, X2 [0032], different than the first distance, as described at [0032].
Regarding claim 5 which depends upon claim 1, Lee teaches the first SiGe regions and the second SiGe regions are concurrently formed at [0035].
Furthermore, Examiner takes the position that even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 777 F.2d 695, 698 (Fed. Cir. 1985). The structure implied by the process steps should be considered when assessing the patentability of product-by-process claims over the prior art, especially where the product can only be defined by the process steps by which the product is made, or where the manufacturing process steps would be expected to impart distinctive structural characteristics to the final product. In re Garnero, 412 F.2d 276, 279 (CCPA 1979). Once the examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. In re Marosi, 710 F.2d 798, 802 (Fed. Cir. 1983). See MPEP 2113. Here the prior art appears to show the same or similar structure and Applicant is invented to comf forward with evidence of an unobvious difference.
Regarding claim 6 which depends upon claim 1, Lee teaches at [0035] and Figure 10A, a source region and a drain region of the first p-FET disposed in the respective first SiGe regions; and a source region and a drain region of the second p-FET disposed in the respective second SiGe regions.
Regarding claim 8 which depends upon claim 1, Lee teaches the first gate dielectric layer and the second gate dielectric layer are concurrently formed at [0021].
Furthermore, Examiner takes the position that even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 777 F.2d 695, 698 (Fed. Cir. 1985). The structure implied by the process steps should be considered when assessing the patentability of product-by-process claims over the prior art, especially where the product can only be defined by the process steps by which the product is made, or where the manufacturing process steps would be expected to impart distinctive structural characteristics to the final product. In re Garnero, 412 F.2d 276, 279 (CCPA 1979). Once the examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. In re Marosi, 710 F.2d 798, 802 (Fed. Cir. 1983). See MPEP 2113. Here the prior art appears to show the same or similar structure and Applicant is invented to comf forward with evidence of an unobvious difference.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 3, 7 and 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Lee and U.S. 2016/0133748 (Kang).
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Regarding claim 3 which depends upon claim 1, Lee does not teach: the first SiGe regions include first portions extended to a first height from the surface of the substrate; and the second SiGe regions include second portions extended to a second height from the surface of the substrate, the second height being different than the first height.
Kang is directed to PMOS transistors. At [0061-62], Kang teaches SiGe is formed in the recess, 105 (see Figure 24) of a transistor source/drain with a composition of Si1-XGex where x ranges from 0.1 to 0.9. Further that with replacement of silicon atoms with Ge atoms, the lattice expands resulting in a compressive channel stress. At [0066], Kang teaches the channel compressive stress is proportional to the thickness of the SiGe layer.
Taken as a whole the prior art is directed to improvements in p-MOS transistor performance. Kang teaches the height of the SiGe source drain regions is proportional to the thickness of the SiGe layer. An artisan would recognize that the compressive stress of the channel modulates the hole mobility and thus produces a transistor with a desired or designed transconductance.
Accordingly it would have been obvious to a person of ordinary skill in the art at the time of Applicant’s invention to configure the device of claim 1, wherein: the first SiGe regions include first portions extended to a first height from the surface of the substrate; and the second SiGe regions include second portions extended to a second height from the surface of the substrate, the second height being different than the first height, to produce a first and second transistor with designed transconductances because doing so is merely a design choice to produce transistors with a desired transconductance, see MPEP 2144, and because the combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
Regarding claim 7 which depends upon claim 1, Lee does not teach: first silicide regions disposed on the first SiGe regions; and second silicide regions disposed on the second SiGe regions.
Kang is directed to improvement in p-MOS transistors. Kang teaches a silicide, 171/173 [0137] formed on SiGe source/drain regions 150 [0135]. At [0142], Kang teaches this structure prevents an increase in contact resistance.
Taken as a whole, the prior art is directed to improvements in p-MOS device performance. Kang teaches a s/d silicide prevents an increase in contact resistance. An artisan would find it desirable to prevent increases in contact resistance to prevent degradation in Fmax for the device.
Accordingly it would have been obvious to a person of ordinary skill in the art at time of Applicant’s invention to configure the device of claim 1, further comprising: first silicide regions disposed on the first SiGe regions; and second silicide regions disposed on the second SiGe regions to prevent an increase in contact resistance thus improving device performance and because the combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
Regarding claim 9 which depends upon claim 1, Lee does not teach the first SiGe regions and the second SiGe regions include a silicon-germanium alloy of Si1-xGex, wherein x varies between 0.2 and 0.5.
Kang is directed to PMOS transistors. At [0061-62], Kang teaches SiGe is formed in the recess, 105 (see Figure 24) of a transistor source/drain with a composition of Si1-XGex where x ranges from 0.1 to 0.9. Further that with replacement of silicon atoms with Ge atoms, the lattice expands resulting in a compressive channel stress. At [0066], Kang teaches the channel compressive stress is proportional to the thickness of the SiGe layer.
Taken as a whole, the prior art is directed to improvements in p-MOS transistors using SiGe source drain regions. Kang teaches that modulation of the germanium concentration modulates the channel stress. An artisan would be familiar with the influence of channel stress on hole mobility, i.e. it increases hole mobility, resulting in a transistor with a high transconductance and is thus a variable to optimize transistor performance, see Kang at [0118]. An artisan would find it desirable to configure a transistor with a high channel stress to improve the electrical performance of the device.
Accordingly, it would have been obvious to a person of ordinary skill in the art at the time of Applicant’s invention to configure the device claim 1, wherein the first SiGe regions and the second SiGe regions include a silicon-germanium alloy of Si1-xGex, wherein x varies between 0.2 and 0.5 to optimize the channel stress and because in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art”, a prima facie case of obviousness exists. In re Woodruff, 919 F.2d 1575 (Fed. Cir. 1990). See MPEP 2144.05. Furthermore, Examiner takes the position that configuration the device of claim 1, wherein the first SiGe regions and the second SiGe regions include a silicon-germanium alloy of Si1-xGex, wherein x varies between 0.2 and 0.5 is merely the combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
Regarding claim 10 which depends upon claim 1, Lee does not explicitly teach at least one of the first gate dielectric layer and the second gate dielectric layer includes a high-k dielectric material having a dielectric constant greater than silicon dioxide (SiO2).
Kang teaches a p-MOS transistor uses a high-k dielectric [0066], which includes silicon nitride [0122].
Taken as a whole, the prior art is directed to p-MOS transistor improvements. An artisan would recognize the use of high-k dielectrics enables transistors to be scaled to lower critical dimensions. An artisan would recognize that high-k dielectrics have a dielectric, e.g. SiN at 7-9 has a dielectric constant greater than silicon dioxide, e.g. 3.9.
Accordingly it would have been obvious to a person of ordinary skill in the art at the time of Applicant’s invention to configure the device of claim 1, wherein at least one of the first gate dielectric layer and the second gate dielectric layer includes a high-k dielectric material having a dielectric constant greater than silicon dioxide SiO2 to scale the transistor to smaller critical dimensions and because the combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
Regarding claim 11 which depends upon claim 1, Lee teaches at [0034];
[0034] At operation 118, the method 100 (FIG. 1B) epitaxially grows source and drain (S/D) features 242a and 242b in the recesses 240a and 240b respectively. Referring to FIGS. 10A and 10B, the S/D features 242a-b fill the recesses 240a-b and further grow above a top surface of the fin active regions 204a-b. In the present embodiment, the S/D features 242a-b are further raised above a top surface of the gate dielectric layer 222. The raised S/D features 242a-b provide stress to the channel region 212a-b for improved device performance. Further, the S/D features 242a are deeper and have a greater volume than the S/D features 242b, which provides a relatively greater stress to the channel region 212a. At the same time, two adjacent S/D features 242b are properly separated from each other (FIG. 10B). Thus, operation 118 satisfies requirements for both logic devices and memory devices simultaneously. One explanation for this phenomenon is as follows. Since the recesses 240b are relatively shallower and smaller, the silicon areas for epitaxial growth are relatively smaller. Therefore, the growth rate of the epitaxial features 242b is relatively slower than the epitaxial features 242a, and when the epitaxial features 242a are properly raised, the epitaxial features 242b still stay separated.
At [0042] Lee teaches
[0042] Although not intended to be limiting, one or more embodiments of the present disclosure provide many benefits to a semiconductor device and the formation thereof. For example, embodiments of the present disclosure provide methods of forming raised epitaxial S/D features for both logic devices and memory devices simultaneously while fulfilling different requirements for the two types of devices. For example, the S/D features in the logic devices have a large volume so as to stress or strain the devices' channel regions for improved carrier mobility while the S/D features in the memory devices may remain separate between adjacent S/D features to avoid unintended circuit shorts. Embodiments of the present disclosure provide the above differences by creating different S/D recess profiles in the two types of devices. A further embodiment creates the different S/D recess profiles using one etching process for the two types of devices rather than separate etching processes. This improves production efficiency.
At Figure 3 Lee teaches a first device region 200a, [0022] and a second device region 200b [0022] which are n and p fet regions respectively and at Figure 10A teaches an n-channel field effect transistor (n-FET) in the substrate, the n-FET being exclusive of a SiGe region, i.e. there is no raised s/d region in the 200b n-fet region [0017]. Lee teaches an n-channel field effect transistor (n-FET) in the substrate the n-FET being exclusive of a SiGe region, at Figure 10A.
Kang teaches an n-channel field effect transistor (n-FET), as annotated [0119], in the substrate, 10 [0120], the n-FET being exclusive of a SiGe region, 150/200 [0119].
Kang teaches at [0158], p-mos transistors are used in a logic circuit as well as a CMOS inverter. Further at [0160] that connecting a n-mos and p-mos device an inverter is formed.
Taken as a whole the prior art is directed to integration of n-mos and p-mos devices. Kang and Lee teach that use of a n-channel FET in the substrate being exclusive of a SiGe region is integrated with p-channel devices to form an inverter. An artisan would recognize an inverter as a key circuit element in an SRAM device. An artisan would recognize that SRAM and logic are concurrently used for CPU devices.
Accordingly, it would have been obvious to a person of ordinary skill in the art at the time of Applicant’s invention to configure the device of claim 1 comprising an n-channel field effect transistor (n-FET) in the substrate, the n-FET being exclusive of the SiGe region to configure an inverter circuit and because the combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
Allowable Subject Matter
Claim 4 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 4 the prior art does not teach the device of claim 1 wherein: the first p-FET includes first lightly-doped drain (LDD) regions laterally extended between the first SiGe regions and the first gate structure; and the second p-FET includes second lightly-doped drain (LDD) regions laterally extended between the second SiGe regions and the second gate structure, the second LDD regions being different than the first LDD regions.
Claims 12-25 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 12 the prior art fails to disclose a method, comprising: depositing a hard mask over a first p-channel field effect transistor (p-FET) structure in a first region of a substrate and a second p-FET structure in a second region of the substrate, wherein— the first p-FET structure includes: a first gate dielectric layer on a surface of the substrate; a first gate structure on the first gate dielectric layer; first spacers formed on sidewalls of the first gate structure; and first source/drain areas of the substrate, on both sides of the first gate structure; and the second p-FET structure includes: a second gate dielectric layer on the surface of the substrate; a second gate structure on the second gate dielectric layer; second spacers formed on sidewalls of the second gate structure; and second source/drain areas of the substrate, on both sides of the second gate structure; forming a first patterned photoresist mask that uncovers the first region to expose the first p-FET structure while covering the second region; performing a first etch process after forming the first patterned photoresist mask, the first etch process configured to remove at least a portion of the hard mask over the first p-FET structure; removing the first patterned photoresist mask; forming a second patterned photoresist mask that uncovers the second region to expose the second p-FET structure while covering the first region; and performing a second etch process after forming the second patterned photoresist mask, the second etch process configured to remove at least a portion of the hard mask over the second p-FET structure, the second etch process different than the first etch process.
Claims 13-25 depend directly or indirectly on claim 12 and are allowable on that basis.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is listed on the notice of references cited.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Joe Schoenholtz whose telephone number is (571)270-5475. The examiner can normally be reached M-Thur 7 AM to 7 PM PST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ms. Yara Green can be reached at (571) 272-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.E. Schoenholtz/Primary Examiner, Art Unit 2893