DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
In addressing the rejection ground, each claim may not have been separately discussed to the extent the claimed features are the same as or similar to the previously-discussed features; the previous discussion is construed to apply for the other claims in the same or similar way.
In the office action, “/” should be read as and/or as generally understood. For example, “A/B” means A and B, or A or B.
Claim Objections
Claims 8, 10-17 and 24-29 are objected to because of the following informalities:
Claim 8, line 11 recites “a control input coupled at least one of the first or second controller outputs”. It should be recited as --a control input coupled to at least one of the first or second controller outputs--.
Claims 10-17 are objected to based on the dependency from claim 8.
Claim 24, line 8 recites “control logic having an input”. It should be recited as --a control logic having an input--.
In addition, claim 24, lines 13-14 recite “coupled to the second terminal of the second transistor the first input of the comparator”. It should be recited as --coupled to the second terminal of the second transistor, the first input of the comparator--.
Claims 25-29 are objected to based on the dependency from claim 24.
. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8, 10-17 and 24-29 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 8 recites “a slope compensation circuit coupled between the inductor terminal and the input of the controller circuit and has a control input coupled at least one of the first or second controller outputs”, which renders the claim indefinite. Neither the specification nor the drawing figures disclose the slope compensation circuit has a control input coupled at least one of the first or second controller outputs.
Claims 10-17 are rejected based on the dependency from claim 8.
Claim 24 recites “a circuit coupled to the second terminal of the second transistor the first input of the comparator and to at least one of the first or second outputs of the control logic”, which renders the claim indefinite. Neither the specification nor the drawing figures disclose the slope compensation circuit is coupled to at least one of the first or second controller outputs.
In addition, claim 24 recites “configurable to provide a first signal…”, which renders the claim indefinite. It is unclear whether the limitation refers to an ability that is required to be present in the invention, whether it refers to an ability can be achieved by modifying the system, whether it refers to a system ability that is not required, or something else.
Claims 25-29 are rejected based on the dependency from claim 24.
Further clarification is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8 and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xi (US 2013/0002223) in view of Fan et al. (US 2018/0248479).
Regarding claim 8 (as best understood), Xi discloses a system [e.g. fig. 3], comprising: a controller circuit [e.g. 301, 303, part of 308/ 302] having an input [e.g. the bottom input of 303/302], and first and second controller outputs; a first driver circuit having a first driver input and a first driver output, wherein the first driver input is coupled to the first controller output; a second driver circuit having a second driver input and a second driver output, wherein the second driver input is coupled to the second controller output; a power stage [e.g. 304] having first and second inputs [inputs to M1. M2] and an inductor terminal [e.g. L], wherein a slope compensation circuit [e.g. 307, 305 (or C1)/302/306] coupled between the inductor terminal and the input of the controller circuit and has a control input [e.g. the top terminal of R2/ the top terminal of C1/ the top terminal of R1] coupled [e.g. output of 303 coupled to the top terminal of R2 via 308, M1/M2, L; or output of 303 coupled to the top terminal of R1/C1 via 308, M1/M2. In light of claim 24, which recites “a first driver circuit; a second driver circuit; control logic having an input, having a first output coupled to the control terminal of the first transistor via the first driver circuit, and having a second output coupled to the control terminal of the second transistor via the second driver circuit”. It appears that coupled is very broad based on the recited phrase.] at least one of the first or second controller outputs. Xi does not disclose driving circuit comprises a pre-driver and two drivers to drive the first gate and the second gate. However, it’s well-known to provide a pre-driver and two drivers to drive a first gate and a second gate. For example, Fan discloses a pre-driver [e.g. 260] and two drivers [e.g. see the two drivers in 270] to drive a first gate [e.g. the high-side gate] and a second gate [the low-side gate], such that the combination discloses a first driver circuit [see the top gate driver circuit in 270 Fan] having a first driver input and a first driver output, wherein the first driver input is coupled to the first controller output [e.g. the input to the first driver Fan]; a second driver circuit [see the bottom gate driver circuit in 270 Fan] having a second driver input and a second driver output [e.g. the input to the second driver Fan], wherein the second driver input is coupled to the second controller output. the first input of the power stage is coupled to the first driver output, and the second input of the power stage is coupled to the second driver output;
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Xi in accordance with the teaching of Fan regarding a switching circuit in order to drive a high-side gate and a low-side gate, respectively.
Regarding claim 24 (as best understood), Xi discloses an apparatus [e.g. fig. 3 Xi] comprising: a first transistor [e.g. M1 Xi] having first [e.g. the top/bottom terminal] and second [e.g. the bottom/top terminal] terminals and a control terminal [e.g. the gate terminal], the first terminal coupled to a voltage supply terminal [e.g. VIN]; a second transistor [e.g. M2] having a second terminal coupled to the second terminal of the first transistor, having a first terminal coupled to a ground terminal [e.g. the ground], and having a control terminal; control logic [ e.g 303/301] having an input; a comparator [e.g. 302] having an output coupled to the input of the control logic, and having a first input [e.g. the bottom input]; and a circuit [e.g. 305, 306, 307] coupled to the second terminal of the second transistor the first input of the comparator and to at least one of the first or second outputs of the control logic [e.g. via driving circuit] and configurable to provide a first signal having a rising slope and a second signal having a falling slope at the first input of the comparator responsive to states of the second terminal of the second transistor and the at least one of the first or second outputs of the control logic.
Xi does not disclose driving circuit comprises a pre-driver and two drivers to drive the first gate and the second gate. However, it’s well-known to provide a pre-driver and two drivers to drive a first gate and a second gate. For example, Fan discloses a pre-driver [e.g. 260] and two drivers [e.g. see the two drivers in 270] to drive a first gate [e.g. the high-side gate] and a second gate [the low-side gate], such that the combination discloses a first driver circuit [see the top gate driver circuit in 270 Fan]; a second driver circuit [see the bottom gate driver circuit in 270 Fan]; control logic having a first output [e.g. the input to the first driver Fan] coupled to the control terminal of the first transistor via the first driver circuit, and having a second output [e.g. the input to the second driver Fan] coupled to the control terminal of the second transistor via the second driver circuit, wherein the second driver input is coupled to the second controller output. the first input of the power stage is coupled to the first driver output, and the second input of the power stage is coupled to the second driver output; and the circuit [e.g. 305, 306, 307] coupled to the second terminal of the second transistor the first input of the comparator and to at least one of the first or second outputs of the control logic [e.g. via the top, bottom driving circuits of Fan]. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Xi in accordance with the teaching of Fan regarding a switching circuit in order to drive a high-side gate and a low-side gate, respectively. Also, see rejection of claim 8.
Response to Arguments
Applicant's arguments filed 11/20/2025 have been fully considered but they are not persuasive.
Applicant argues that claims 8, and 10-17 and 24-29 are allowable. However, the scopes of the independent claims 8 and 24 have been changed. Please see the rejections of claims 8 and 24 under 35 USC § 103 and 35 USC § 112.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PATRICK C CHEN whose telephone number is (571)270-7207. The examiner can normally be reached M-F Flexible 9:00-5:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lincoln Donovan can be reached at 571-272-1988. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PATRICK C CHEN/Primary Examiner, Art Unit 2842