The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 5-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Rubin et al. (U.S. Patent Application Publication 2023/0197705, hereinafter referred to as Rubin).
As to claim 1, Rubin teaches 1. A device comprising: a first circuit [105 in Fig. 7] comprising a first side, the first side comprising a first region and a second region, the first circuit comprising a first interconnect; a second circuit [150F in Fig. 7] coupled to the first region, the second circuit being coupled to the first circuit through the first interconnect; a third circuit [150F2 in Fig. 7] coupled to the second region, the third circuit being coupled to the first circuit through the first interconnect; a second interconnect coupled to the third circuit; and a fourth circuit [750 in Fig. 7] coupled to the third circuit through the second interconnect.
As to claim 2, Rubin teaches 2. The device of claim 1, further comprising a first memory coupled to the second circuit, the second circuit comprising a second memory. [150F in Fig. 7]
As to claim 5, Rubin teaches 5. The device of claim 1, further comprising an interposer comprising the second interconnect. [¶0061, 0079]
As to claim 6, Rubin teaches 6. The device of claim 1, wherein the fourth circuit comprises a processor. [¶0039]
As to claim 7, Rubin teaches 7. The device of claim 1, wherein the first circuit is coupled to the second circuit by hybrid copper bonding. [¶0079]
As to claim 8, Rubin teaches 8. The device of claim 1, wherein the first circuit is coupled to the third circuit by hybrid copper bonding. [¶0079]
As to claim 9, Rubin teaches 9. The device of claim 1, wherein the third circuit comprises a first physical layer circuit. [¶0085]
As to claim 10, Rubin teaches 10. The device of claim 9, wherein the fourth circuit comprises a second physical layer circuit, the first physical layer circuit is coupled to the second physical layer circuit through the second interconnect. [¶0085]
As to claim 11, Rubin teaches 11. The device of claim 1, wherein: the first side comprises a metal layer; and the first circuit further comprises a second side, the second side comprises a silicon layer. [¶0077]
As to claim 12, Rubin teaches 12. The device of claim 1, wherein the first interconnect comprises a bus operating at a first speed and the first circuit comprises a logic circuit operating at a second speed, the first speed being higher than the second speed. [¶0044; 0079]
As to claim 13, Rubin teaches 13. The device of claim 12, wherein: the third circuit comprises a gearbox circuit; the fourth circuit operates at a third speed; and the gearbox circuit is configured to match the first speed to the third speed. [¶0044; 0079]
As to claim 14, Rubin teaches 14. The device of claim 1, further comprising a die coupled to the third circuit. [Fig. 7~8]
As to claim 15, Rubin teaches 15. A device comprising: a first circuit [105] comprising a first side and a second side, the first side comprising a first region and a second region, the first circuit comprising a first interconnect; a second circuit coupled to the first region, the second circuit [150F] being coupled to the first circuit through the first interconnect; a third circuit [150F2] coupled to the second region, the third circuit [150N] being coupled to the first circuit through the first interconnect; an interposer [405] coupled to the second side; and a fourth circuit [750] coupled to the third circuit through the interposer. [see Fig. 7]
As to claim 16, Rubin teaches 16. The device of claim 15, wherein the first side comprises a metal layer, and the second side comprises a silicon layer. [¶0077]
As to claim 17, Rubin teaches 17. The device of claim 15, wherein the third circuit comprises a first physical layer circuit, the fourth circuit comprises a second physical layer circuit, and the first physical layer circuit is coupled to the second physical layer circuit through the interposer. [¶0085; 0087]
As to claim 18, Rubin teaches 18. The device of claim 15, wherein the first circuit is coupled to the second circuit by hybrid copper bonding. [¶0079]
As to claim 19, Rubin teaches 19. A device comprising: a first circuit comprising a first side, the first side comprising a first region and a second region, the first circuit comprising a first interconnect; a second circuit coupled to the first region, the second circuit being coupled to the first circuit through the first interconnect; a third circuit coupled to the second region, the third circuit comprising a first physical layer circuit; a second interconnect coupled to the third circuit; and a fourth circuit comprising a second physical layer circuit, the second physical layer circuit being coupled to the first physical layer circuit through the second interconnect. [see 105, 150F, 150F2, 750 in Fig. 7]
As to claim 20, Rubin teaches 20. The device of claim 19, wherein the first interconnect comprises a bus operating at a first speed and the first circuit comprises a logic circuit operating at a second speed, the first speed being higher than the second speed. [¶0044; 0079]
Claim Rejections - 35 USC § 103
1. The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
2. Claim 3-4 rejected under 35 U.S.C. 103(a) as being unpatentable over Rubin in view of Dokania et al. (U.S. Patent Application Publication 23230059491, hereinafter referred to as Dokania).
As to claim 3, Rubin may not explicitly teach 3. The device of claim 2, wherein the first memory circuit comprises a first through silicon via (TSV) and the second memory circuit comprises a second TSV, the first TSV being coupled to the second TSV through a micro bump.
Dokania teaches this limitation [¶0077 for example]
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to combine the teachings of Rubin and Dokania to “use TSV" in Rubin according to Dokania, for the further advantage of “utilizing known method of coupling stacked dies”. [..FIG. 3B illustrates a cross-section of a package 320 where compute die 303 is below memory die 304, where compute die 303 is perforated with high-density through-silicon vias (TSVs) to couple with the bumps between compute die 303 and memory die 304…¶0077]
As to claim 4, Rubin and Dokania teaches 4. The device of claim 1, wherein the third circuit comprises a driver. [¶0088 Dokania]
Conclusion
Claims 1-20 are rejected as explained above.
The prior art made of record in the PTO-892 form and not relied upon is considered pertinent to applicant's disclosure.
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/JAEHWAN OH/
Primary Examiner, Art Unit 2899