DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-3, 7-13, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yazawa (U.S. Publication No. 2018/0226341 A1) in view of Totoki et al. (U.S. Publication No. 2022/0130852 A1; hereinafter Totoki)
With respect to claim 1, Yazawa discloses an integrated circuit device comprising: a substrate [10] comprising a memory cell area and a connection area (see Figure 16); a gate stack on the substrate and comprising a plurality of gate electrodes [21] that are apart from each other in a vertical direction with a plurality of gate connection openings defined in the connection area [50] (see Figure 7) to extend inward from an upper surface of the gate stack, one of the plurality of gate electrodes being exposed at a bottom surface of each of the plurality of gate connection openings (see Figure 7); a plurality of gate connection structures [41/42] respectively covering at least inner side surfaces of the plurality of gate connection openings (see Figure 1B), each of the plurality of gate connection structures being connected with the one of the plurality of gate electrodes (See Figure 1B); Yazawa fails to disclose a plurality of gate contacts respectively connected to upper ends of the plurality of gate connection structures.
In the same field of endeavor, Totoki teaches a plurality of gate contacts [86A/B] respectively connected to upper ends of the plurality of gate connection structures [82/84] (See Figure 21). Implementation of gate contacts as taught by Totoki facilitate connections between the gate connections within the memory device to external chip structures (see ¶[0099]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 2, the combination of Yazawa and Totoki discloses wherein the connection area further defines a plurality of stack openings (see Yazawa Figure 1A) arranged in the connection area to extend inward from the upper surface of the gate stack, and the integrated circuit device further comprises a plurality of spacer insulating layers [42] respectively covering inner side surfaces of the plurality of stack openings and respectively defining the plurality of gate connection openings (See Figure 1B).
With respect to claim 3, the combination of Yazawa and Totoki discloses a plurality of channel structures [60] passing through the gate stack in the memory cell area (see Totoki Figure 21); and a plurality of dummy structures apart from the plurality of channel structures and passing through the gate stack, wherein at least one of the plurality of dummy structures is arranged in each of the plurality of gate connection openings and is covered by each of the plurality of gate connection structures (see Yazawa Figure 16; contact structure is divided into 4 parts, creating redundancies that are not functionally necessary, therefore can be considered dummy structures).
With respect to claim 7, the combination of Yazawa and Totoki discloses wherein the plurality of gate connection structures extend from the bottom surfaces of the plurality of gate connection openings to uppermost ends of the plurality of gate connection openings along the inner side surfaces of the plurality of gate connection openings, respectively (See Yazawa Figure 1B).
With respect to claim 8, the combination of Yazawa and Totoki discloses wherein the plurality of gate connection structures at least partly fill the plurality of gate connection openings, respectively (See Yazawa Figure 1B).
With respect to claim 9, the combination of Yazawa and Totoki discloses wherein the plurality of gate contacts are respectively and electrically connected with the plurality of gate electrodes through the plurality of gate connection structures (see Totoki Figure 21), and the plurality of gate contacts, which are respectively and electrically connected with the plurality of gate electrodes that are at different vertical levels from each other, have a same vertical height (see Totoki Figure 21).
With respect to claim 10, the combination of Yazawa and Totoki discloses wherein the gate stack comprises a plurality of memory cell blocks [100] and has no stepwise structure (see Totoki Figure 21; no stepwise structure in memory cell blocks), each of the plurality of memory cell blocks being surrounded by a gate stack separation opening that passes through the gate stack (See Totoki Figure 21). Implementation of a no stepwise structure accommodates an increased density of memory structure as taught by Totoki (Figure 21). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 11, Yazawa discloses an integrated circuit device comprising: a substrate [10] comprising a memory cell area and a connection area (see Figure 16); a gate stack on the substrate and comprising a plurality of insulating layers [22] and a plurality of gate electrodes [21], which are alternately arranged in a vertical direction; a plurality of structures [40] passing through the gate stack in the memory cell area with a plurality of gate connection openings [50] defined in the connection area to extend inward from an upper surface of the gate stack, one of the plurality of gate electrodes being exposed at a bottom surface of each of the plurality of gate connection openings; a plurality of dummy structures apart from the plurality of structures and passing through the gate stack (see Yazawa Figure 16; contact structure is divided into 4 parts, creating redundancies that are not functionally necessary, therefore can be considered dummy structures), at least one of the plurality of dummy structures being arranged in each of the plurality of gate connection openings (See Figure 16); a plurality of gate connection structures [41/42] conformally covering inner side surfaces of and bottom surfaces of the plurality of gate connection openings, respectively, wherein each of the plurality of gate connection structures is connected with the one of the plurality of gate electrodes, which is exposed at the bottom surface of each of the plurality of gate connection openings, and covers the at least one of the plurality of dummy structures arranged in each of the plurality of gate connection openings; Yazawa fails to disclose a plurality of channel structures and wherein a plurality of gate contacts respectively connected to upper ends of the plurality of gate connection structures. In the same field of endeavor, Totoki teaches a plurality of channel structures [60] passing through the gate stack in the memory cell area with a plurality of gate connection openings (see Figure 21) and wherein a plurality of gate contacts [86A/B] respectively connected to upper ends of the plurality of gate connection structures [GC] (See Figure 21).
Channel structures within the gate connection structures as taught by Totoki facilitates memory storage within the vertical structures of the memory device (See Totoki ¶[0070]). Furthermore, implementation of gate contacts as taught by Totoki facilitate connections between the gate connections within the memory device to external chip structures (see Totoki ¶[0099]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 12, the combination of Yazawa and Totoki discloses a plurality of spacer insulating layers [22] each between each of the plurality of gate connection structures and a gate electrode [21] above the one gate electrode, which is exposed at the bottom surface of each of the plurality of gate connection openings from among the plurality of gate electrodes (see Yazawa Figure 5).
With respect to claim 13, the combination of Yazawa and Totoki discloses wherein each of the plurality of spacer insulating layers is between two insulating layers adjacent to each other in the vertical direction from among the plurality of insulating layers (see Yazawa Figure 5).
With respect to claim 18, the combination of Yazawa and Totoki discloses wherein the plurality of gate contacts have a same vertical height (See Totoki Figure 21).
Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Totoki in view of Yazawa.
With respect to claim 19, Totoki discloses an electronic system comprising: a main substrate [10]; an integrated circuit device [100/300] on the main substrate; and a controller on the main substrate (see ¶[0078]) and electrically connected with the integrated circuit device, wherein the integrated circuit device comprises, a gate stack comprising a plurality of gate electrodes [146], which are apart from each other in a vertical direction on a substrate comprising a memory cell area [100] and a connection area [300] (See Figure 21), a plurality of channel structures [60] passing through the gate stack in the memory cell area with a plurality of gate connection openings defined in the connection area to extend inward from an upper surface of the gate stack (see Figure 21), each of the plurality of gate connection structures [82/84] being connected with the one gate electrode (See Figure 21), and a plurality of gate contacts [86A/B] respectively connected to upper ends of the plurality of gate connection structures (see Figure 21).
Totoki fails to disclose one of the plurality of gate electrodes being exposed at a bottom surface of each of the plurality of gate connection openings, a plurality of dummy structures apart from the plurality of channel structures and passing through the gate stack, at least one of the plurality of dummy structures being arranged in each of the plurality of gate connection openings, a plurality of gate connection structures respectively covering inner side surfaces and bottom surfaces of the plurality of gate connection openings. In the same field of endeavor, Yazawa teaches one of the plurality of gate electrodes [21] being exposed at a bottom surface of each of the plurality of gate connection openings [50] (see Figure 5), a plurality of dummy structures apart from the plurality of channel structures and passing through the gate stack, at least one of the plurality of dummy structures being arranged in each of the plurality of gate connection openings (see Yazawa Figure 16; contact structure is divided into 4 parts, creating redundancies that are not functionally necessary, therefore can be considered dummy structures ¶[0041-0045]), a plurality of gate connection structures [40] respectively covering inner side surfaces and bottom surfaces of the plurality of gate connection openings (see Figure 1B). Implementation of a high aspect ratio gate connection structure as well as an integrated dummy structure as taught by Yazawa allows for increased contact and maintaining size while increasing memory capacity (See Yazawa ¶[0030]). Integration of dummy structures within the gate connection structures allows for redundancies within already formed gate connection openings, simplifying manufacturing and accounting for possible manufacturing failures (See ¶[0030] and ¶[0043]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 20, the combination of Totoki and Yazawa discloses wherein the plurality of gate connection structures extend from the bottom surfaces of the plurality of gate connection openings to uppermost ends of the plurality of gate connection openings along the inner side surfaces of the plurality of gate connection openings, respectively, and the plurality of gate contacts have a same vertical height (see Totoki Figure 21).
Allowable Subject Matter
Claims 4-6 and 14-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to claims 4-6, none of the prior art teaches or suggests, alone or in combination, wherein the at least one of the plurality of dummy structures comprises a loss dummy structure having an upper end below those of upper ends of other dummy structures not arranged in the plurality of gate connection openings.
With respect to claims 14-17, none of the prior art teaches or suggests, alone or in combination, wherein the at least one of the plurality of dummy structures in each of the plurality of gate connection openings passes through the one gate electrode connected with each of the plurality of gate connection structures respectively in the plurality of gate connection openings.
Conclusion
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/JONATHAN HAN/Primary Examiner, Art Unit 2818