DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgement of Amendment
Amendment filed 08/18/26 for the application has been acknowledged.
Applicant cancelled Claims 1-9 that were earlier withdrawn from consideration as directed to a non-chosen invention, amended Claims 10, 15-16, 18-20, and added new Claims 22-26.
Status of Claims
Claims 10-26 are pending in the application and are examined on merits herein.
Claim Rejections – 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10-14, 16-19, 21, and 24-26 are rejected under 35 U.S.C. 103 as being unpatentable over Saito et al. (JP 2012064630) in view of Yuan et al. (CN 216413071).
In re Claim 10, Saito teaches a package, comprising (Fig. 6B, page 2- two last paragraphs and page 3 – two first paragraphs):
first 201a and second 201b dies including first 201a and second 201b diodes, respectively;
first 207a and second 207b metal contacts (if made similar electrode 107 of Fig. 6A, page 2, paragraph 4) physically contacting a substrate of the first 201a and second 201b dies, respectively,
a bond wire 208 coupled to top surfaces of the first 201a and second 201b dies, the top surfaces of the first and second dies opposing the bottom surfaces of the first and second dies; and
a mold compound 210 covering the first 201a and second 201b dies and the bond wire 208, the mold compound 210 contacting the first 207a and second 207b metal contacts.
Saito does not teach that the first and second metal contacts are visible from a bottom surface of the package, since these metal contacts are attached to metal islands 209a and 209b, and only the metal islands are visible from the bottom surface of the package.
Yuan teaches (Fig. 1, page 6 paragraphs 1-2 and page 7 – an underline sentence of paragraph 4) a diode package in which electrode 11, directly contacting a diode substrate is exposed from a mold.
Saito and Yuan teach analogous arts related to metal contacts for semiconductor components, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Saito device in view of the Yuan device, since they are from the same field of endeavor, and Yuan created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Saito device by creating it without islands 209a and 209b while exposing the first and second metal contacts from the bottom surface of the package, wherein it is desirable to directly connect the first and second metal contacts to other circuits (Yuan, page 7 last paragraph and page 8 first paragraph).
In re Claim 11, Saito/Yuan teaches the package of Claim 10 as cited above, wherein the first and second metal contacts are not part of a lead frame.
In re Claim 12, Saito/Yuan teaches the package of Claim 10 as cited above, wherein, as shown for Claim 10, the first and second metal contacts are applied to the bottom surfaces of the first and second dies by a metal deposition technique – being a vacuum evaporation technique (Saito, page 2, paragraph 4).
In re Claim 13, Saito/Yuan teaches the package of Claim 12 as cited above, wherein the metal deposition technique is physical vapor deposition (PVD) or chemical vapor deposition (CVD): As is known in the art, the vacuum evaporation technique includes such methods as PVD and CVD – see paragraph 0076 of Fure e al (US 2003/0015517) or paragraph 0105 of Momoda et al. (US 2007/0127133).
In re Claim 14, Saito/Yuan teaches the package of Claim 10 as cited above, wherein the package lacks a die attach layer – Saito or Yuan do(es) not teach such a layer.
In re Claim 16, Saito teaches a package, comprising (Fig. 6B, page 2- two last paragraphs and page 3 – two first paragraphs):
first 201a and second 201b dies including first 201a and second 201b diodes, respectively;
first 207a and second 207b metal contacts (if made similar electrode 107 of Fig. 6A, page 2, paragraph 4) coupled to bottom surfaces of the first 201a and second 201b dies, respectively, each of the first and second metal contacts having substantially a same cross-sectional width as the first and second dies respectively, where the first and second metal contacts have physical properties indicating that the first and second metal contacts were formed by deposition on the bottom surfaces of the first and second dies (obviously, see page 2 paragraph 4),
a bond wire 208 coupled to top surfaces of the first 201a and second 201b dies, the top surfaces of the first and second dies opposing the bottom surfaces of the first and second dies; and
a mold compound 210 covering the first 201a and second 201b dies and the bond wire 208, the mold compound 210 contacting the first 207a and second 207b metal contacts.
Saito does not teach that the package lacks a conductive die attach layer – he does teach dies attached layer that comprises islands 209a and 209b.
Yuan teaches (Fig. 1, page 6 paragraphs 1-2 and page 7 – an underline sentence of paragraph 4) a diode package in which electrode 11, directly contacting a diode substrate, is not attached to a conductive layer.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Saito device by creating it without die attached layer 209a and 209b while exposing the first and second metal contacts from the bottom surface of the package, wherein it is desirable to directly connect the first and second metal contacts to other circuits (Yuan, page 7 last paragraph and page 8 first paragraph).
In re Claim 17, Saito/Yuan teaches the package of Claim 16 as cited above, wherein, as is shown for Claim 16, the first and second metal contacts are not obtained from a lead frame.
In re Claim 18, Saito/Yuan teaches the package of Claim 16 as cited above, wherein the first and second metal contacts are formed by physical vapor deposition (PVD): Saito teaches (page 2 paragraph 4) a vapor deposition method (for creating contact 107 of Fig. 6A, and it would have been obvious creating contacts 207a and 207b of Fig. 6B with a same method), which inherently includes a PVD method – see paragraph 0076 of Fure e al (US 2003/0015517) or paragraph 0105 of Momoda et al. (US 2007/0127133).
In re Claim 19, Saito/Yuan teaches the package of Claim 16 as cited above, wherein the first and second metal contacts are formed by chemical vapor deposition (CVD): Saito teaches (page 2 paragraph 4) a vapor deposition method (for creating contact 107 of Fig. 6A, and it would have been obvious creating contacts 207a and 207b of Fig. 6B with a same method), which inherently includes a CVD method – see paragraph 0076 of Fure e al (US 2003/0015517) or paragraph 0105 of Momoda et al. (US 2007/0127133).
In re Claim 21, Saito/Yuan teaches the package of Claim 16 as cited above, wherein Saito teaches (page 2 and two top paragraphs of page 3) that the package is an electrostatic discharge device (ESD)
In re Claim 24, Saito teaches a package, comprising (Fig. 6B, page 2- two last paragraphs and page 3 – two first paragraphs):
first semiconductor die 201a and second semiconductor die 201b, each die having a front surface and a back surface, each die comprising a diode;
a backside metal layer – comprising metal contacts 207a and 207b (if made similar electrode 107 of Fig. 6A, page 2, paragraph 4) contacting a substrate of each die,
a bond wire 208 electrically connecting the front surface of the first semiconductor die to the front surface of the second semiconductor die, and
an encapsulant body mold 210 surrounding the first 201a and the second semiconductor 201b semiconductor dies and the bond wire 208.
Saito does not teach that the back surface metal layer of each die is flush with and exposed at a bottom surface of the encapsulant body, since another metal layer 209a/209b is attached to the backside metal layer and is flush with and exposed at the bottom surface of the encapsulant body.
Yuan teaches (Fig. 1, page 6 paragraphs 1-2 and page 7 – an underline sentence of paragraph 4) a diode package in which electrode 11 is flush with and exposed at a bottom surface of an encapsulant body.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Saito device by creating it without die attached layer 209a/209b while creating the backside layer 207a/207b flush with and exposed at the bottom surface of the package, wherein it is desirable creating the package such that its backside metal would be directly connected to other circuits (Yuan, page 7 last paragraph and page 8 first paragraph).
In re Claim 24, Saito/Yuan teaches the package of Claim 24 as cited above, wherein Saito teaches (page 2 and two top paragraphs of page 3) that the package is an electrostatic discharge device (ESD)
In re Claim 26, Saito/Yuan teaches the package of Claim 24 as cited above and wherein (Saito, Fig. 6B) the backside meta layer 207a and 207b includes a same cross-sectional width of each die.
Claims 15 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Saito/Yuan in view of an ESD diode specification (NPL, attached to the previous Office Action).
In re Claims 15 and 20, Saito/Yuan teaches the packages of Claims 10 and 16 as cited above, but does not teach that the first die – the first ESD diode - has a length and width between 100 um and 1000 um – no information on the length and width of the ESD diode is provided.
The ESD diode specification (created for the ESD diode by Texas Instruments in 2016) teaches that a length and a width of the ESD diode (page 1 in section 3 Description) is in a range from 300 um to 600 um.
Saito/Yuan and “ESD diode specification” are from the same field of endeavor directed to ESD diodes, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Saito/Yuan diode in view of the above specification, since they are from the same field of endeavor, and the ESD diode specification refers to the ESD diodes successfully used in the art.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to create the Saito/Yuan diodes of Claims 10 and 15 with a length and a width in the range from 100 um to 1000 um, since ESD diodes with such dimensions are needed in the art. See MPEP 2144.05 Obviousness of Similar and Overlapping Ranges, Amounts, and Proportions. I. OVERLAPPING, APPROACHING, AND SIMILAR RANGES, AMOUNTS, AND PROPORTIONS: In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Saito/Yuan in view of Wang et al. (CN 116404064).
In re Claim 22, Saito/Yuan teaches the package of Claim 10 as cited above, but does not explicitly teach that the first and second metal contacts include a thickness in the range of 1 um to 15 um: though Saito makes it obvious (page 7, paragraph 2) that the above thickness is less than 10 um, Saito does not teach a lowest value of the range.
Wang teaches (Fig. 1, Claim 3) that a width of a metal contact is from 0.1 um to 0.3 um.
Saito/Yuan and Wang teach analogous arts related to metal contacts for semiconductor elements, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Saito/Yuan device in view of the Wang device, since they are from the same field of endeavor, and Wang created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Saito/Yuan package of Claim 10 by creating its first and second metal contacts with a thickness in the range from 0.1 um to 10 um (per Saito and Wang), in order to enable creation of such parameter of the metal contacts as their thickness. See MPEP 2144.05 Obviousness of Similar and Overlapping Ranges, Amounts, and Proportions. I. OVERLAPPING, APPROACHING, AND SIMILAR RANGES, AMOUNTS, AND PROPORTIONS: In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Response to Arguments
Applicant arguments (REMARKS, filed 08/18/26) have been fully considered.
Examiner agrees with Applicant (Remarks, page 5) that a set of amended claims have no grounds for rejection under 35 U.S.C. 112(b)/
Examiner agrees with Applicant that amended independent Claims 10 and 16 cannot be rejected using such combination of prior arts as Sito and Wang, but disagrees that the claims are patentable – the current Office Action shows that a new combination of prior arts teaches all limitations of the amended Claims 10 and 16. Same applies to a new independent Claim 24 (REMARKS, page 6).
As such, Examiner disagrees with patentability of examined claims of the application (REMARKS, pages 6-7).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication should be directed to GALINA G YUSHINA whose telephone number is 571-270-7440. The Examiner can normally be reached between 8 AM - 7 PM Pacific Time (Flexible).
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/GALINA G YUSHINA/Primary Patent Examiner, Art Unit 2811, TC 2800,
United States Patent and Trademark Office
E-mail: galina.yushina@USPTO.gov
Phone: 571-270-7440
Date: 08/27/26
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