Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Attorney Docket Number: 8947-001890-US
Filling Date: 10/31/23
Priority Date: 12/19/22
Inventor: Kim et al
Examiner: Bilkis Jahan
DETAILED ACTION
1. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status
Claim Rejections - 35 USC § 102
2. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
3. Claim(s) 10-13 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lai et al (US 2019/0312050 A1).
Regarding claim 10, Lai discloses a semiconductor device (Figs. 2 and 16), comprising: a gate stack including insulating 215, 225, 235 (Para. 35) and conductive patterns 211, 221, 231 (Para. 35), which are alternately stacked on top of each other; a memory channel structure 216, 217 (Para. 36) penetrating the gate stack (Fig. 2A); a selection line structure 271, 272 (Para. 35) on the gate stack; and a selection channel structure 293, 236, 237 (Para. 45) penetrating the selection line structure 271, 272, wherein
the memory channel structure comprises an insulating capping layer 218 (Para. 36, air gap is insulating), a memory channel layer 216, 217 (Para. 36) enclosing the insulating capping layer 218, and a memory layer 1610, 1605 (Para. 66, Fig. 16) enclosing the memory channel layer 216, 217, the selection channel structure 293, 236, 237 comprises a selection channel layer 236, 237 (Para. 45) electrically connected to the memory channel layer 216, 217, and a selection insulating structure 286 (Para. 42) enclosing the selection channel layer 236, 237 the selection channel layer 236, 237 comprises a connecting portion 219 (Para. 36) on the memory channel structure 216, 217 and a pillar portion 239 (Para. 45) on the connecting portion 219, and the pillar portion 239 overlaps with a center of the selection channel structure 293, 236, 237.
Regarding claim 11, Lai discloses the semiconductor device of claim 10, wherein the pillar portion has a pillar shape 239.
Regarding claim 12, Lai discloses the semiconductor device of claim 10, wherein the selection channel structure 293, 236, 237 further comprises a selection channel pad 248 (Para. 45) on the selection channel layer 236, 237, and the selection channel layer 236, 237 and the selection channel pad 248 fill a space (Fig. 2A) that is enclosed by the selection insulating structure 286.
Regarding claim 13, Lai discloses the semiconductor device of claim 10, wherein the selection insulating structure 286 (left, Para. 42) comprises a first selection insulating pattern 286 enclosing the selection channel layer 236, 237, a second selection insulating pattern 286 (right) enclosing the first selection insulating pattern 286, and a third selection insulating pattern 287 (Para. 41) enclosing the second selection insulating pattern 286.
Regarding claim 18, Lai discloses the semiconductor device of claim 10, wherein the pillar portion 239 is overlapped with a center line of the selection channel structure 236, 237.
Allowable Subject Matter
4. Claims 14-16 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
5. Claims 1-9, 19 and 20 are allowed.
6. The following is an examiner’s statement of reasons for allowance:
7. The applied prior arts neither anticipate nor render the claimed subject matter obvious because they fail to teach the claimed semiconductor device, comprising: a connecting portion on the memory channel structure and a pillar portion on the connecting portion, and an average size of grains in the connecting portion is less than an average size of grains in the pillar portion in combination with all other limitations as recited in claim 1.
8. The applied prior arts neither anticipate nor render the claimed subject matter obvious because they fail to teach the claimed electronic system, comprising: a pillar portion on the connecting portion, the pillar portion overlaps with a center of the selection channel structure, when viewed in a plan view, a width of the connecting portion is larger than a width of the pillar portion, the selection channel layer comprises polysilicon, and an average size of grains in the connecting portion is less than an average size of grains in the pillar portion in combination with all other limitations as recited in claim 19.
9. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BILKIS JAHAN whose telephone number is (571)270-5022. The examiner can normally be reached Monday-Friday, 8:00 am-5 Pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon T Fletcher can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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BILKIS . JAHAN
Primary Examiner
Art Unit 2817
/BILKIS JAHAN/Primary Examiner, Art Unit 2817
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