DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
In light of the amendment filed 5/19/26, the rejection of the claims under 35 U.S.C. 112(a) is withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 9, and 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2019/0311662) in view of Gao et al. (US 2021/0209979) and Song et al. (US 2021/0286002).
Regarding claim 1, Kim discloses a display device comprising: a substrate including: a display area in which a plurality of sub-pixels is arranged; and a non-display area disposed around the display area (abstract, figs. 1-4, ¶ 61-68, display area DA and non-display area NDA);
a demux circuit portion disposed in the non-display area on the substrate and including: a first switching transistor including a part of a first lower gate pattern (figs. 1-2, ¶ 61-68, see also ¶ 75, demultiplexer 240, e.g., TC1 with gate connected to CS1);
a second switching transistor including a part of a second lower gate pattern (figs. 1-2, ¶ 61-68, see also ¶ 75, e.g., TC2 with gate connected to CS2);
a first control line which is connected to the first lower gate pattern and supplies a first lighting test control signal or a first demux control signal (figs. 1-2, ¶ 61-68, see also ¶ 75, demultiplexer 240, e.g., TC1 with gate connected to CS1);
and a second control line which is connected to the second lower gate pattern and supplies a second lighting test control signal or a second demux control signal (figs. 1-2, ¶ 61-68, see also ¶ 75, e.g., TC2 with gate connected to CS2);
and a lighting circuit portion electrically connected to the demux circuit portion and including: a third switching transistor (figs. 1-2, ¶ 61-68, see also ¶ 73-81, test circuits 220 and 260, e.g., T2 with gate connected to TCS2);
and a fourth switching transistor which is directly connected to third sub-pixels of the plurality of sub-pixels (figs. 1-2, ¶ 61-68, see also ¶ 73-81, e.g., T3 with gate connected to TCS3),
and a fifth switching transistor including a part of a third lower gate pattern (figs. 1-2, ¶ 61-68, see also ¶ 73-81, e.g., T1 with gate connected to TCS1),
wherein a first terminal of the first switching transistor and a first terminal of the second switching transistor are electrically connected to a transmission line electrically connected to a data driver (figs. 1-2, ¶ 61-69, TC1 and TC2 electrically connected to CL; see also see also ¶ 73-81; see also figs. 6-8),
and a second terminal of the first switching transistor and a second terminal of the second switching transistor are electrically connected to the third switching transistor and the fourth switching transistor, respectively (figs. 1-2, ¶ 61-68, TC1 and TC2 electrically connected to T2 and T3; see also see also ¶ 73-81),
and are not directly connected to each other in a state in which the first switching transistor and the second switching transistor are turned off (figs. 1-2, ¶ 61-68, e.g., terminals of TC1 and TC2 not directly connected to CL are not directly connected when TC1 and TC2 are off).
Kim fails to disclose a third switching transistor which is directly connected to first and second sub-pixels of the plurality of sub-pixels, includes another part of the first lower gate pattern and receives the first lighting test control signal through the first control line; a fourth switching transistor which includes another part of the second lower gate pattern and receives the second lighting test control signal through the second control line, and a fifth switching transistor directly connected to the first and second sub-pixels of the plurality of sub-pixels.
Gao teaches a third switching transistor which includes another part of the first lower gate pattern and receives the first lighting test control signal through the first control line (figs. 10-16, see ¶ 75-80, switches of the display test unit 73 and switches of the demultiplexer 30 share control lines; see also ¶ 108-111);
and a fourth switching transistor which includes another part of the second lower gate pattern and receives the second lighting test control signal through the second control line (figs. 10-16, see ¶ 75-80, switches of the display test unit 73 and switches of the demultiplexer 30 share control lines; see also ¶ 108-111).
Kim and Gao are both directed to displays with demultiplexer and test circuits. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Kim with the shared control lines of Gao since such a modification reduces the number of control signal lines and saves the space occupied by the non-display area (Gao, ¶ 79).
Song teaches a third switching transistor which is directly connected to first and second sub-pixels of the plurality of sub-pixels (figs. 2 and 4, ¶ 43-47, e.g., T2),
and a fifth switching transistor directly connected to the first and second sub-pixels of the plurality of sub-pixels (figs. 2 and 4, ¶ 43-47, e.g., T1).
Kim in view of Gao and Song are both directed to displays with test circuits. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Kim in view of Gao with the test circuit of Song since such a modification provides integrated test circuits (Song, ¶ 5) and provides a reduced dead space, reduced bezel, and an elegant design (Song, ¶ 103).
Regarding claim 2, Kim discloses wherein the lighting circuit portion further includes: a third control line which is connected to the third lower gate pattern and supplies a third lighting test control signal (figs. 1-2, ¶ 61-68, see also ¶ 73-81, e.g., T1 with gate connected to TCS1).
Regarding claim 3, Kim discloses wherein the third lower gate pattern is spaced apart from the first and second lower gate patterns (figs. 1-2, ¶ 61-68, see also ¶ 73-81, e.g., T1 with gate connected to TCS1 spaced apart from T2 and T3).
Regarding claim 4, Kim discloses wherein the demux circuit portion and the lighting circuit portion share a circuit area in which the third, fourth, and fifth switching transistors are disposed (figs. 1-2, ¶ 61-68, non-display area NDA , see also ¶ 73-81).
Regarding claim 9, Kim discloses wherein the lighting circuit portion further includes: a first lighting test signal line which is connected to the third switching transistor and supplies a first lighting test signal (figs. 1-2, ¶ 61-68, see also ¶ 73-81, DC2);
a second lighting test signal line which is connected to the fourth switching transistor and supplies a second lighting test signal (figs. 1-2, ¶ 61-68, see also ¶ 73-81, DC3);
and a third lighting test signal line which is connected to the fifth switching transistor and supplies a third lighting test signal (figs. 1-2, ¶ 61-68, see also ¶ 73-81, DC1).
Regarding claim 11, Kim discloses wherein the first and second sub-pixels includes: a blue sub-pixel which emits blue light; and a red sub-pixel which emits red light, and the third sub-pixels include a green sub-pixel which emits green light (figs. 1-2, ¶ 61-72, red, blue, and green disclosed).
Regarding claim 12, Kim discloses wherein the third switching transistor transmits the first lighting test signal to the blue sub-pixel in response to the first lighting test control signal (figs. 1-3, ¶ 72-81, DC2 transmitted through T2 to B pixel),
the fourth switching transistor transmits the second lighting test signal to the green sub-pixel in response to the second lighting test control signal (figs. 1-3, ¶ 72-81, DC3 transmitted through T3 to G pixel),
and the fifth switching transistor transmits the third lighting test signal to the red sub-pixel in response to the third lighting test control signal (figs. 1-3, ¶ 72-81, DC1 transmitted through T1 to R pixel).
Regarding claim 13, Kim discloses wherein the first switching transistor transmits a data voltage to the red sub-pixel and the blue sub-pixel in response to the first demux control signal (figs. 1-3, ¶ 67, see also ¶ 72-81, TC1 connected to data line with B and R sub-pixel),
and the second switching transistor transmits the data voltage to the green sub-pixel in response to the second demux control signal (figs. 1-3, ¶ 67, see also ¶ 72-81, TC2 connected to data line with G sub-pixel).
Regarding claim 14, Kim discloses wherein the lighting circuit portion is disposed between the display area and the demux circuit portion in a plan view (figs. 1-2, ¶ 61-70).
Regarding claim 15, Kim discloses a data driver which is electrically connected to the demux circuit portion and generates a data voltage, wherein the demux circuit portion divides and outputs the data voltage to at least two data lines (figs. 1-3, ¶ 67-69, see also fig. 6).
Regarding claim 16, this claim is rejected under the same rationale as claim 1.
Regarding claim 17, this claim is rejected under the same rationale as claim 2.
Regarding claim 18, this claim is rejected under the same rationale as claim 9.
Regarding claim 19, this claim is rejected under the same rationale as claims 11 and 12.
Regarding claim 20, this claim is rejected under the same rationale as claim 13.
Claims 5-8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Gao and Song as applied to claims 2 and 9 above, and further in view of Wei et al. (US 2023/0148233).
Regarding claim 5, Kim in view of Gao and Song fails to explicitly disclose an active layer disposed in the non-display area on the substrate, constituting a semiconductor layer of each of the first, second, third, fourth, and fifth switching transistors, and including: a first active pattern and a second active pattern spaced apart from the first active pattern and including a first part and a second part forming at least an empty space therebetween.
Wei teaches an active layer disposed in the non-display area on the substrate, constituting a semiconductor layer of each of the first, second, third, fourth, and fifth switching transistors (fig. 3, active layer 111, see ¶ 88, see also ¶ 203-219, active layer 212 of multiplexing transistors and active layer 312 of test transistors disposed in the same layer as layer 111; see also figs. 6 and 13),
and including: a first active pattern and a second active pattern spaced apart from the first active pattern and including a first part and a second part forming at least an empty space therebetween (fig. 3, active layer 111, see ¶ 88, see also ¶ 203-219, active layer 212 of multiplexing transistors and active layer 312 of test transistors spaced apart and disposed in the same layer as layer 111; see also figs. 6 and 13).
Kim in view of Gao and Song and Wei are both directed to displays with demultiplexer and test circuits. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Kim in view of Gao and Song with the active layer of Wei since such a modification provides simplified structures that may be directly provided on a display substrate (Wei, ¶ 2).
Regarding claim 6, Wei further teaches wherein the first lower gate pattern partially overlaps each of the first active pattern, the first part of the second active pattern, and the second part of the second active pattern (fig. 3, gate electrode 112, see ¶ 88, see also ¶ 203-219, figs. 6 and 13, gate electrodes 211/311),
the second lower gate pattern partially overlaps each of the first active pattern, the first part of the second active pattern, and the second part of the second active pattern (fig. 3, gate electrode 112, see ¶ 88, see also ¶ 203-219, figs. 6 and 13, gate electrodes 211/311),
and the third lower gate pattern partially overlaps the second part of the second active pattern (fig. 3, gate electrode 112, see ¶ 88, see also ¶ 203-219, figs. 6 and 13, gate electrodes 211/311).
Regarding claim 7, Wei further teaches wherein the first switching transistor further includes a part of the first active pattern and a part of the first part of the second active pattern, and the second switching transistor further includes another part of the first active pattern and another part of the first part of the second active pattern (fig. 3, active layer 111, see ¶ 88, see also ¶ 203-219, active layer 212 of multiplexing transistors spaced apart and disposed in the same layer as layer 111; see also figs. 6 and 13).
Regarding claim 8, Wei further teaches wherein the third switching transistor further includes a part of the second part of the second active pattern, the fourth switching transistor further includes another part of the second part of the second active pattern, and the fifth switching transistor further includes another part of the second part of the second active pattern (fig. 3, active layer 111, see ¶ 88, see also ¶ 203-219, active layer 312 of test transistors spaced apart and disposed in the same layer as layer 111; see also figs. 6 and 13).
Regarding claim 10, Kim discloses a data connection line which is connected to each of the first and second switching transistors and supplies a data voltage (figs. 1-3, ¶ 67-69, connecting lines CL, see also ¶ 72-81).
Kim in view of Gao and Song fails to disclose an intermediate bridge pattern connected to the third lighting test signal line through a contact hole; and an upper bridge pattern connected to each of the third lighting test signal line and the data connection line through a contact hole.
Wei teaches an intermediate bridge pattern connected to the third lighting test signal line through a contact hole (fig. 3, see ¶ 88, e.g., part of source and drain electrodes 113/114, see also ¶ 203-219, electrical connection realized by via holes see also figs. 6 and 13);
and an upper bridge pattern connected to each of the third lighting test signal line and the data connection line through a contact hole (fig. 3, see ¶ 88, e.g., upper part of source and drain electrodes 113/114, see also ¶ 203-219, electrical connection realized by via holes see also figs. 6 and 13).
Kim in view of Gao and Song and Wei are both directed to displays with demultiplexer and test circuits. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Kim in view of Gao and Song with the device of Wei since such a modification provides simplified structures that may be directly provided on a display substrate (Wei, ¶ 2).
Response to Arguments
Applicant’s arguments filed 5/19/26 with respect to claim(s) 1 and 16 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEITH L CRAWLEY whose telephone number is (571)270-7616. The examiner can normally be reached Monday - Friday 10-6 ET.
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/KEITH L CRAWLEY/Primary Examiner, Art Unit 2626
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