DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-6 in the reply filed on 2/24/26 is acknowledged.
Claims 7-14 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 2/24/26.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) were submitted on 10/31/23 and 3/03/26. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2, 5 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kawashiro (US PGPub 2021/0035893, hereinafter referred to as “Kawashiro”) in view of Shearer et al. (WO 2016/174584 hereinafter referred to as “Shearer”).
Kawashiro discloses the semiconductor method substantially as claimed. See figures 1-10 and corresponding text, where Inaba teaches, in claim 1, a method of manufacturing a semiconductor device, the method comprising: (figure 1; [0021-0046])
a step (a) of manufacturing a semiconductor module (100) by sealing, with a mold resin (86), a first metal plate (16), an insulating layer (12) bonded to a lower surface of the first metal plate (16), a second metal plate (20) bonded to a lower surface of the insulating layer (12), and a semiconductor element (24) mounted on an upper surface of the first metal plate (16) with a first bonding member (30) between the semiconductor element (24) and the first metal plate (16) in a state in which a lower surface of the second metal plate (20) is exposed; and
a step (b) of mounting the semiconductor module (100) on a metal base plate (2) ([0025], metal) by bonding the lower surface of the second metal plate (20) to an upper surface of the metal base plate (2) by a second bonding member (32) having a melting point lower than a melting point of the first bonding member (30), ([0040], melting points) wherein the step (b) includes steps of disposing the semiconductor module (100) on the upper surface of the metal base plate (2) with the second bonding member (32) between the semiconductor module (100) and the metal base plate (2), heating the metal base plate (2), the second bonding member (32), and the semiconductor module (100) to melt the second bonding member (32), and then cooling the metal base plate (2), the second bonding member (32), and the semiconductor module (100) to cure the second bonding member (32), and during the cooling of the metal base plate, the second bonding member (32), and the semiconductor module (100), a difference between an upper surface temperature of the metal base plate (2) and a lower surface temperature of the first metal plate (16) (figure 2; [0047-0058]).
However, Kawashiro fails to show, in claim 1, during cooling of the metal base a difference between the upper surface temperature of the metal base plate and a lower temperature of the first metal plate at a solid phase line of the second bonding member is 5° C. or less.
Shearer teaches, claim 1, teaches a similar device that includes a eutectic solder that includes bismuth-based alloys to attach (20) an electronic component (40) to a substrate (70) (figure 1; [0089-0090]). In addition, Shearer teaches the cooling rate temperature to be less than 6oC per second between about 2.17 and about 3.25 oC per minute ([0053]). Also, Shearer teaches selecting the cooling rate from the peak temperature of the profile to room temperature to prevent damage to the semiconductor chip as a result of thermal shock ([0053]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate during cooling of the metal base a difference between the upper surface temperature of the metal base plate and a lower temperature of the first metal plate at a solid phase line of the second bonding member is 5° C. or less, in the method of Kawashiro, according to the teachings Shearer, with the motivation of preventing damage to the semiconductor chip from thermal shock.
Kawashiro in view of Shearer shows, in claim 2, wherein the second bonding member is tin solder containing bismuth, and during the cooling of the metal base plate, the second bonding member, and the semiconductor module, a difference between an upper surface temperature of the metal base plate and a lower surface temperature of the first metal plate at a eutectic point of the second bonding member in a case of containing the bismuth at 58% is 2° C. or less ([0053], taught by Shearer).
Kawashiro in view of Shearer shows, in claim 5, wherein a plurality of pin fins protruding downward are provided on a lower surface of the metal base plate, and in the step (b), the metal base plate, the second bonding member, and the semiconductor module are cooled by bringing a cooling block into contact with tips of the plurality of pin fins (figure 1, [0022-0025], taught by Kawashiro).
Kawashiro in view of Shearer shows, in claim 6, wherein a plurality of pin fins protruding downward are provided on a lower surface of the metal base plate, and in the step (b), the metal base plate, the second bonding member, and the semiconductor module are cooled by bringing a cooling block into contact with tips of the plurality of pin fins (figure 1, [0022-0025], taught by Kawashiro).
Claim(s) 3 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kawashiro (US PGPub 2021/0035893, hereinafter referred to as “Kawashiro”) in view of Shearer et al. (WO 2016/174584 hereinafter referred to as “Shearer”) as applied to claim 1 above, and further in view of Mohamed et al. (US PGPub 2017/0365544, hereinafter referred to as “Mohamed”).
Kawashiro in view of Shearer discloses the semiconductor method substantially as claimed. See the rejection above.
However, Kawashiro in view of Shearer fails to show, in claim 3, wherein in the step (b), the metal base plate, the second bonding member, and the semiconductor module are cooled by blowing a cooled reducing gas from above the semiconductor module.
Mohamed teaches, in claim 3, an attaching apparatus that includes a cooling zone that controls the temperature in a nitrogen gas environment (figures 1 and 3C; [0023], [0036-0037]). In addition, Mohamed provides the advantages of providing high reliability connections ([0003]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention filed, to incorporate wherein in the step (b), the metal base plate, the second bonding member, and the semiconductor module are cooled by blowing a cooled reducing gas from above the semiconductor module, in the method of the Kawashiro in view of Shearer, according to the teachings of Mohamed, with the motivation of providing high reliability connections.
Kawashiro in view of Shearer fails to show, in claim 4, wherein in the step (b), the metal base plate, the second bonding member, and the semiconductor module are cooled by blowing a cooled reducing gas from above the semiconductor module.
Mohamed teaches, in claim 4, an attaching apparatus that includes a cooling zone that controls the temperature in a nitrogen gas environment (figures 1 and 3C; [0023], [0036-0037]). In addition, Mohamed provides the advantages of providing high reliability connections ([0003]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention filed, to incorporate wherein in the step (b), the metal base plate, the second bonding member, and the semiconductor module are cooled by blowing a cooled reducing gas from above the semiconductor module, in the method of the Kawashiro in view of Shearer, according to the teachings of Mohamed, with the motivation of providing high reliability connections.
Conclusion
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/STANETTA D ISAAC/Examiner, Art Unit 2898 April 4, 2026
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