DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This Non-Final office action is in response to application 18/499,026, application filed on 10/31/2023. Claims 1-20 are currently pending in this application.
Information Disclosure Statement
3. The information disclosure statement (IDS) submitted on 02/01/2024 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
5. Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Cantwell (US PG Pub No. 2024/0037442).
6. With respect to independent claims 1 and 8, Cantwell teaches:
receiving, at a computing system, physics constraints related to a real-world process (see physics-based model, para 25; see physics based constraints, para 33);
receiving, at the computing system, historical samples corresponding to previous iterations of the real-world process (see historical sensor data, para 39; historical manufacturing data, para 40; historical parameters, para 39-40);
performing, using a digital twin at the computing system, artificial intelligence (AI) synthesis to generate synthesized samples for the real-world process based on the physics constraints and the historical samples (see digital twin model, para 79; physics-physics-based digital twin model, para 83, 123-124);
performing the real-world process to generate real-world samples (see samples of training set, para 189); and
combining the synthesized samples with the real-world samples (see combination of data sets, para 22; see combination of sensor data, metrology data, manufacturing parameters, predictive component, para 40-45; defecting manufacturing physics-based model, par 40-45).
7. With respect to independent claim 15, Cantwell teaches:
receiving, at a computing system, faults identified on a first integrated circuit (IC) (manufacturing fault, para 40-45; substrate manufacturing fault, para 80-83);
receiving, at the computing system, an IC design for a new IC (see new substrate model, samples, para 180-185); and
performing, using a digital twin at the computing system, artificial intelligence (AI) synthesis to generate synthesized design samples for the new IC based on the identified faults and the IC design (see updated substrate design, para 182; see artificial neural network, para 75).
8. With respect to claims 2 and 9, Cantwell teaches:
wherein the real-world process is a process in at least one of semiconductor fabrication or manufacturing an electronic device (see realistic image of substrate, para 100).
9. With respect to claims 3 and 10, Cantwell teaches:
wherein the real-world process comprises testing a semiconductor wafer to determine a fault, wherein the historical samples are generated by testing previous semiconductor wafers, wherein the physics constraints comprise testing parameters for testing the semiconductor wafer (see semiconductor wafers, para 21; see samples of semiconductor wafer physical parameters and models, para 25).
10 With respect to claims 4 and 11, Cantwell teaches:
analyzing the combined synthesized samples and real-world samples to determine whether additional testing should be performed on the semiconductor wafer (see additional testing, verification, modeling of wafers/semiconductor process, para 62-65).
11. With respect to claims 5 and 12, Cantwell teaches:
wherein data generated by the previous iterations of the real-world process is clustered into clusters, the method further comprising: receiving a selection of a subset of the clusters to use as the historical samples (see cluster, para 37-40; see subsets of values for property features for simulation/modeling, para 55).
12. With respect to claims 6 and 13, Cantwell teaches:
receiving samples in a first domain, wherein the AI synthesis is performed using the samples in the first domain, wherein the synthesized samples are in a second domain, wherein the first domain is a different data type than the second domain (see sampling, different set of substrate parameters/conditions, new input conditions, para 20-25; see different wafers, para 39-42).
13. With respect to claims 7 and 14, Cantwell teaches:
wherein the samples in the first domain comprises at least one of design diagrams of a semiconductor wafer and the synthesized samples comprises physical substrate samples of the semiconductor wafer (see sampling, different set of substrate parameters/conditions, new input conditions, para 20-25; see different wafers, para 39-42).
14. With respect to claim 16, Cantwell teaches:
manufacturing the new IC based on the synthesized design samples (see new substrate model, samples, para 180-185).
15. With respect to claim 17, Cantwell teaches:
analyzing the new IC to identify faults (see new updated substrate, baseline values, fault/defect, para 180-185); and
feeding back the identified faults for the new IC to the AI synthesis to generate updated synthesized design samples for the new IC (see artificial neural network, para 74-79); and
manufacturing the new IC based on the updated synthesized design samples (see sampling, different set of substrate parameters/conditions, new input conditions, para 20-25; see different wafers, para 39-42)
16. With respect to claim 18, Cantwell teaches:
wherein manufacturing the new IC based on the synthesized design samples comprising
manufacturing different variants of the new IC (see new updated substrate, baseline values, fault/defect, para 180-185)),
analyzing the different variants to identify faults (manufacturing fault, para 40-45; substrate manufacturing fault, para 80-83), and
feeding back the identified faults for the variants to generate the updated synthesized design samples for the new IC (see artificial neural network, para 74-79).
17. With respect to claim 19, Cantwell teaches:
receiving, at the computing system, a related IC design, wherein the related IC design corresponds to a circuit block in the IC design for the new IC that is not in the first IC (see new updated substrate, baseline values, fault/defect, para 180-185).
18. With respect to claim 20, Cantwell teaches:
wherein the first IC is an older version of a device and the new IC is a newer version of the device, wherein the related IC design corresponds to a different device (see new updated substrate, baseline values, fault/defect, para 180-185).
Conclusion
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/SUCHIN PARIHAR/
Primary Examiner, Art Unit 2851
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