DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11 and 12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 recites the limitation "the single surface passivation layer" in the last two lines. There is insufficient antecedent basis for this limitation in the claim. Due to its dependency, claim 12 is also rejected.
For purposes of examination, the examiner has interpreted "the single surface passivation layer" in claim 11 to mean the upper surface passivation sub-layer.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 9, 10, 13, 16, 20, and 23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kajitani et al. (United States Patent Application Publication No. US 2015/0194483 A1, hereinafter “Kajitani”).
In reference to claim 1, Kajitani discloses a structure which meets the claim. Fig. 4A-4M of Kajitani discloses a semiconductor device which comprises a semiconductor substrate (201, 202, 203) with an upper surface and a channel (203). Source (205) and drain (206) electrodes are over the upper surface of the semiconductor substrate (201, 202, 203). The source (205) and drain (206) electrodes are electrically coupled to the channel (203). The channel (203) extends between the source (205) and drain (206) electrodes. A surface passivation (207) is over the upper surface of the semiconductor substrate (201, 202, 203) between the source (205) and drain (206) electrodes. A first interlayer dielectric (214) is over an upper surface of the surface passivation (207). A gate electrode (212) is over the upper surface of the semiconductor substrate (201, 202, 203) is between the source (205) and drain (206) electrodes. The gate electrode (212) includes a gate channel portion that extends through the surface passivation (207) to contact the upper surface of the semiconductor substrate (201, 202, 203), a first gate field plate (212 – note lowest lateral portion in direct contact with 209) with a first horizontal bottom extent that overlies the upper surface of the surface passivation (207), and a second gate field plate (212 – note highest lateral portion in direct contact with 209) with a second horizontal bottom extent that is higher than the first horizontal bottom extent. A conductive field plate (208, 213) is over the upper surface of the semiconductor substrate (201, 202, 203) is between the gate electrode (212) and the drain electrode (206). The conductive field plate (208, 213) includes a first field plate (208) with a third horizontal bottom extent that overlies and contacts the upper surface of the surface passivation (207). There is a second field plate (213) with a fourth horizontal bottom extent (213 – rightmost portion with bottom surface in direct contact with 209) that is at least as high as the first horizontal bottom extent of the first gate field plate (212 – note lowest lateral portion in direct contact with 209).
With regard to claim 2, there is a horizontal dielectric spacer portion (209) on an upper surface of the surface passivation (207). The fourth horizontal bottom extent (213 – rightmost portion with bottom surface in direct contact with 209) of the second field plate (213) overlies and contacts an upper surface of the horizontal dielectric spacer portion (209).
In reference to claim 3, the conductive field plate (208, 213) includes a third plate with a fifth horizontal bottom extent (213 – portion with bottom surface in direct contact with 208) that is higher than the fourth horizontal bottom extent (213 – rightmost portion with bottom surface in direct contact with 209) of the second field plate (213).
With regard to claim 9, the surface passivation (207) consists of a single surface passivation layer (207) formed on the upper surface of the semiconductor substrate (201, 202, 202). An upper surface of the single surface passivation layer (207) defines the upper surface of the surface passivation (207). The third horizontal bottom extent of the first field plate (208) contacts the upper surface of the single surface passivation layer (207).
In reference to claim 10, the single surface passivation layer (207) is formed of aluminum oxide, aluminum nitride, and silicon nitride (p. 4, paragraph 101, p. 4-5, paragraph 114).
With regard to claim 13, the first field plate (208) and the second field plate (213) are formed from a field plate metal (p. 4, paragraphs 102 and 105, p. 4-5, paragraph 114. The semiconductor device further comprises a source metallization (not shown in figures but disclosed – p. 4, paragraph 108, p. 5, paragraph 123) that extends from the field plate metal over the gate electrode to a source contact.
In reference to claim 16, Kajitani discloses a method which meets the claim. Fig. 4A-4M of Kajitani discloses a method of fabricating a semiconductor device which comprises a providing a semiconductor substrate (201, 202, 203) with an upper surface and a channel (203). A surface passivation (207) is formed over the upper surface of the semiconductor substrate (201, 202, 203). A first interlayer dielectric (214) is formed over an upper surface of the surface passivation (207). Source (205) and drain (206) electrodes are formed over the upper surface of the semiconductor substrate (201, 202, 203). The source (205) and drain (206) electrodes are electrically coupled to the channel (203). The channel (203) extends between the source (205) and drain (206) electrodes. A gate electrode (212) is formed over the upper surface of the semiconductor substrate (201, 202, 203) is between the source (205) and drain (206) electrodes. The gate electrode (212) includes a gate channel portion that extends through the surface passivation (207) to contact the upper surface of the semiconductor substrate (201, 202, 203), a first gate field plate (212 – note lowest lateral portion in direct contact with 209) with a first horizontal bottom extent that overlies the upper surface of the surface passivation (207), and a second gate field plate (212 – note highest lateral portion in direct contact with 209) with a second horizontal bottom extent that is higher than the first horizontal bottom extent. A conductive field plate (208, 213) is formed over the upper surface of the semiconductor substrate (201, 202, 203) between the gate electrode (212) and the drain electrode (206). The conductive field plate (208, 213) includes a first field plate (208) with a third horizontal bottom extent that overlies and contacts the upper surface of the surface passivation (207). There is a second field plate (213) with a fourth horizontal bottom extent (213 – rightmost portion with bottom surface in direct contact with 209) that is at least as high as the first horizontal bottom extent of the first gate field plate (212 – note lowest lateral portion in direct contact with 209).
With regard to claim 20, forming the conductive field plate (208, 213) includes forming it with a third plate with a fifth horizontal bottom extent (213 – portion with bottom surface in direct contact with 208) that is higher than the fourth horizontal bottom extent (213 – rightmost portion with bottom surface in direct contact with 209) of the second field plate (213).
In reference to claim 23, the forming the surface passivation (207) consists of forming a single surface passivation layer (207) on the upper surface of the semiconductor substrate (201, 202, 202). An upper surface of the single surface passivation layer (207) defines the upper surface of the surface passivation (207).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Kajitani.
So far as understood in claim 11, the surface passivation (207) of Kajitani is a single surface passivation layer. Kajitani does not explicitly disclose forming two surface passivation layers. However it would have been obvious to one having ordinary skill in the art at the time the invention was made to form additional surface passivation layers, since it has been held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). Therefore this limitation is not patentable over Kajitani. In the device of Kajitani constructed in view of the above, there are two surface passivation layers with a lower surface passivation layer formed on the upper surface of the semiconductor substrate (201, 202, 203) and an upper surface passivation layer (207) formed on the lower surface passivation layer, wherein an upper surface of the upper surface passivation layer (207) defines the upper surface of the surface passivation and the third horizontal bottom extent of the first field plate (208) contacts the upper surface of the upper surface passivation layer (207).
In reference to claim 24, the surface passivation (207) of Kajitani is a single surface passivation layer. Kajitani does not explicitly disclose forming two surface passivation layers. However it would have been obvious to one having ordinary skill in the art at the time the invention was made to form additional surface passivation layers, since it has been held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). Therefore this limitation is not patentable over Kajitani. In the method of Kajitani constructed in view of the above, there are two surface passivation layers formed with a lower surface passivation layer formed on the upper surface of the semiconductor substrate (201, 202, 203) and an upper surface passivation layer (207) formed on the lower surface passivation layer, wherein an upper surface of the upper surface passivation layer (207) defines the upper surface of the surface passivation.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Kajitani as applied to claim 11 above and further in view of Kajitani.
So far as understood in claim 12, as noted above in the rejection of claim 11, in the device of Kajitani constructed in view of the above case law, there are two surface passivation layers but there is no disclosure that the upper surface passivation layer is made of silicon nitride while the lower surface passivation layer is made of aluminum oxide or aluminum nitride. However Kajitani discloses that aluminum oxide, aluminum nitride, and silicon nitride are known passivation layer materials (p. 4, paragraph 101, p. 4-5, paragraph 114). The applicant is reminded in this regard that it has been held that the selection of a known material based on its suitability for its intended use would be entirely obvious. See Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) ("Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.). See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960) (selection of a known plastic to make a container of a type made of plastics prior to the invention was held to be obvious). See MPEP 2144.07. In view of the above, it would therefore be obvious to implement an upper surface passivation layer made of silicon nitride and a lower surface passivation layer made of aluminum oxide or aluminum nitride.
Claims 13-15, 25, and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Kajitani in view of Kobayashi et al. (United States Patent Application Publication No. US 2013/0280877 A1, hereinafter “Kobayashi”).
In reference to claim 13, the first field plate (208) and the second field plate (213) of fig. 4A-4M of Kajitani are formed from a field plate metal (p. 4, paragraphs 102 and 105, p. 4-5, paragraph 114). Kajitani discloses (p. 4, paragraph 108, p. 4-5, paragraph 114) that a source metallization is connected to the field plate metal (208, 213) to a source contact (205). Kajitani does not disclose that the source metallization extends over the gate electrode. However Kobayashi discloses that forming a source metallization connected to a field plate that extends over the gate electrode can reduce excessive leakage current which is desirable in the art (p. 1, paragraph 5). In view of Kobayashi, it would therefore be obvious to implement the source metallization so that it extends over the gate electrode.
With regard to claim 14, Kajitani discloses that the field plate metal includes titanium, aluminum, and gold (p. 4, paragraphs 102 and 105, p. 4-5, paragraph 114). Kajitani also discloses that the source metallization includes gold (p. 4, paragraph 108, p. 4-5, paragraph 114).
In reference to claim 15, the first field plate (208) and the second field plate (213) of fig. 4A-4M of Kajitani are formed from a field plate metal (p. 4, paragraphs 102 and 105, p. 4-5, paragraph 114). Kajitani discloses (p. 4, paragraph 108, p. 4-5, paragraph 114) that a source metallization is connected to the field plate metal (208, 213) to a source contact (205). Kajitani does not disclose that the first field plate (208), the second field plate (213), and the source metallization are one single continuous metallization layer. The examiner would like to note that such an issue (i.e., the integration of multiple pieces into one piece or conversely, using multiple pieces in replacing a single piece) has been previously decided by the courts:
In Howard v. Detroit Stove Works, 150 U.S. 164 (1893), the Court held, "it involves no invention to cast in one piece an article which has formerly been cast in two pieces and put together...."
Also in In re Larson, 144 USPQ 347 (CCPA 1965), the term "integral" did not define over a multi-piece structure secured as a single unit. More importantly, the court went further and stated, "we are inclined to agree with the solicitor that the use of a one-piece construction instead of the [multi-piece] structure disclosed in Tuttle et al. would be merely a matter of obvious engineering choice" (bracketed material added). The court cited In re Fridolph for support.
In re Fridolph, 135 USPQ 319 (CCPA 1962), deals with submitted affidavits relating to this issue. The underlying issue in In re Fridolph was related to the end result of making a multi-piece structure into a one-piece structure. Generally, favorable patentable weight was accorded if the one-piece structure yielded results not expected from the modification of the two-piece structure into a single piece structure.
Therefore, it would have been obvious to one of ordinary skill in the art to integrally form the first field plate (208), the second field plate (213), and the source metallization as one single continuous metallization layer since it is "merely a matter of obvious engineering choice" as set forth in the above case law.
Kajitani discloses that the source metallization includes gold (p. 4, paragraph 108, p. 4-5, paragraph 114). Kajitani does not disclose that the source metallization extends over the gate electrode. However Kobayashi discloses that forming a source metallization connected to a field plate that extends over the gate electrode can reduce excessive leakage current which is desirable in the art (p. 1, paragraph 5). In view of Kobayashi, it would therefore be obvious to implement the source metallization so that it extends over the gate electrode.
In reference to claim 25, forming the conductive field plate includes forming the first field plate (208) and the second field plate (213) of fig. 4A-4M of Kajitani from a field plate metal (p. 4, paragraphs 102 and 105, p. 4-5, paragraph 114). Kajitani discloses (p. 4, paragraph 108, p. 4-5, paragraph 114) forming a source metallization from the field plate metal (208, 213) to a source contact (205). Kajitani does not disclose that forming the source metallization such that it extends over the gate electrode. However Kobayashi discloses that forming a source metallization connected to a field plate that extends over the gate electrode can reduce excessive leakage current which is desirable in the art (p. 1, paragraph 5). In view of Kobayashi, it would therefore be obvious to form the source metallization so that it extends over the gate electrode.
In reference to claim 26, forming the conductive field plate includes forming the first field plate (208) and the second field plate (213) of fig. 4A-4M of Kajitani from a field plate metal (p. 4, paragraphs 102 and 105, p. 4-5, paragraph 114). Kajitani discloses (p. 4, paragraph 108, p. 4-5, paragraph 114) forming a source metallization from the field plate metal (208, 213) to a source contact (205). Kajitani does not disclose that the first field plate (208), the second field plate (213), and the source metallization are one single continuous metallization layer. The examiner would like to note that such an issue (i.e., the integration of multiple pieces into one piece or conversely, using multiple pieces in replacing a single piece) has been previously decided by the courts:
In Howard v. Detroit Stove Works, 150 U.S. 164 (1893), the Court held, "it involves no invention to cast in one piece an article which has formerly been cast in two pieces and put together...."
Also in In re Larson, 144 USPQ 347 (CCPA 1965), the term "integral" did not define over a multi-piece structure secured as a single unit. More importantly, the court went further and stated, "we are inclined to agree with the solicitor that the use of a one-piece construction instead of the [multi-piece] structure disclosed in Tuttle et al. would be merely a matter of obvious engineering choice" (bracketed material added). The court cited In re Fridolph for support.
In re Fridolph, 135 USPQ 319 (CCPA 1962), deals with submitted affidavits relating to this issue. The underlying issue in In re Fridolph was related to the end result of making a multi-piece structure into a one-piece structure. Generally, favorable patentable weight was accorded if the one-piece structure yielded results not expected from the modification of the two-piece structure into a single piece structure.
Therefore, it would have been obvious to one of ordinary skill in the art to integrally form the first field plate (208), the second field plate (213), and the source metallization as one single continuous metallization layer since it is "merely a matter of obvious engineering choice" as set forth in the above case law.
Kajitani does not disclose that the source metallization extends over the gate electrode. However Kobayashi discloses that forming a source metallization connected to a field plate that extends over the gate electrode can reduce excessive leakage current which is desirable in the art (p. 1, paragraph 5). In view of Kobayashi, it would therefore be obvious to implement the source metallization so that it extends over the gate electrode.
Allowable Subject Matter
Claims 4-8, 17-19, 21, and 22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: in the examiner’s opinion, it would not be obvious to implement a semiconductor device which comprises a semiconductor substrate with an upper surface and a channel, source and drain electrodes over the upper surface of the semiconductor substrate such that the source and drain electrodes are electrically coupled to the channel which extends between the source and drain electrodes, surface passivation over the upper surface of the semiconductor substrate between the source and drain electrodes, a first interlayer dielectric (ILD0) over an upper surface of the surface passivation; a gate electrode over the upper surface of the semiconductor substrate between the source and drain electrodes such that the gate electrode includes a gate channel portion that extends through the surface passivation to contact the upper surface of the semiconductor substrate, a first gate field plate with a first horizontal bottom extent that overlies the upper surface of the surface passivation, and a second gate field plate with a second horizontal bottom extent that is higher than the first horizontal bottom extent, and a conductive field plate over the upper surface of the semiconductor substrate between the gate electrode and the drain electrode such that the conductive field plate includes a first field plate with a third horizontal bottom extent that overlies and contacts the upper surface of the surface passivation, a second field plate with a fourth horizontal bottom extent that is at least as high as the first horizontal bottom extent of the first gate field plate, a third field plate with a fifth horizontal bottom extent that is higher than the fourth horizontal bottom extent of the second field plate in combination with the specific interlayer dielectric structure described by the applicant in claim 4. In the examiner’s opinion, it would not be obvious to implement a method of fabricating a semiconductor device which comprises providing a semiconductor substrate with an upper surface and a channel, forming surface passivation over the upper surface of the semiconductor substrate, forming a first interlayer dielectric (ILD0) over an upper surface of the surface passivation, forming source and drain electrodes over the upper surface of the semiconductor substrate such that the source and drain electrodes are electrically coupled to the channel which extends between the source and drain electrodes, forming a gate electrode over the upper surface of the semiconductor substrate between the source and drain electrodes such that the gate electrode includes a gate channel portion that extends through the surface passivation to contact the upper surface of the semiconductor substrate, a first gate field plate with a first horizontal bottom extent that overlies the upper surface of the surface passivation, and a second gate field plate with a second horizontal bottom extent that is higher than the first horizontal bottom extent, and forming a conductive field plate over the upper surface of the semiconductor substrate between the gate electrode and the drain electrode such that the conductive field plate includes a first field plate with a third horizontal bottom extent that overlies and contacts the upper surface of the surface passivation, and a second field plate with a fourth horizontal bottom extent that is at least as high as the first horizontal bottom extent of the first gate field plate in combination with the specific steps of the field plate dielectric spacer formation, the gate dielectric spacer formation, and the interlayer dielectric structure formation as described by the applicant in claims 17, 18, and 21.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEVIN QUINTO whose telephone number is (571)272-1920. The examiner can normally be reached Monday-Friday, 9-5:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KEVIN QUINTO/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893