DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 4-8 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, because the specification, while being enabling for a gate electrode with a first gate field plate and a second gate field plate, does not reasonably provide enablement for a gate electrode with a third field plate. The specification does not enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make or use the invention commensurate in scope with these claims. Amended independent claim 4 recites a gate electrode with a third field plate. The currently filed specification only appears to support a gate electrode with first and second gate field plates and not a gate electrode with an additional third field plate.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 9-11, 13-16, and 23-26 are rejected under 35 U.S.C. 103 as being unpatentable over Moens et al. (USPN 9,741,840 B1, hereinafter “Moens”) in view of Puglisi et al. (United States Patent Application Publication No. US 2012/0261720 A1, hereinafter “Puglisi”) and further in view of Xia et al. (United States Patent Application Publication No. US 2017/0018617 A1, hereinafter “Xia”).
In reference to claim 1, Moens discloses a similar structure. Fig. 14A of Moens discloses a semiconductor device which comprises a semiconductor substrate (102, 106, 122) with an upper surface and a channel (122). Source (622) and drain (624) electrodes are over the upper surface of the semiconductor substrate (102, 106, 122). The source (622) and drain (624) electrodes are electrically coupled to the channel (122). The channel (122) extends between the source (622) and drain (624) electrodes. A surface passivation (164, 166) is over the upper surface of the semiconductor substrate (102, 106, 122) between the source (622) and drain (624) electrodes. A first interlayer dielectric (720) is over an upper surface of the surface passivation (164, 166). The first interlayer dielectric (720) includes a field plate opening that exposes a portion of the upper surface of the surface passivation (164, 166). A gate electrode (1426) is over the upper surface of the semiconductor substrate (102, 106, 122) is between the source (622) and drain (624) electrodes. The gate electrode (1426) includes a gate channel portion that extends through the surface passivation (164, 166) to contact the upper surface of the semiconductor substrate (102, 106, 122), a first gate field plate (1426 – note lowest lateral portion in direct contact with 166) with a first horizontal bottom extent that overlies the upper surface of the surface passivation (164, 166), and a second gate field plate (1426 – note highest lateral portion in direct contact with 720) with a second horizontal bottom extent that is higher than the first horizontal bottom extent. A conductive plate (1457) is over the upper surface of the semiconductor substrate (102, 106, 122) and is between the gate electrode (1426) and the drain electrode (624). Moens does not describe the conductive material (1457) as a conductive field plate. However the examiner would like to note that the elements must be arranged as required by the claim, but this is not an ipsissimis verbis test, i.e., identity of terminology is not required. See In re Bond, 910 F.2d 831, 15 USPQ2d 1566 (Fed. Cir. 1990). Although Moens does not specifically use the term, “conductive field plate,” it is not required in order for the Moens reference to teach this limitation in the claim. Thus this limitation is not patentable over Moens. The conductive field plate (1457) includes a first field plate (1457 – note lowest lateral portion in direct contact with 166) within the field plate opening in the first interlayer dielectric (720) with a third horizontal bottom extent that overlies and contacts the upper surface of the surface passivation (164, 166). There is a second field plate (1457 – note highest lateral portion in direct contact with 720) with a fourth horizontal bottom extent that is at least as high as the first horizontal bottom extent of the first gate field plate 1426 – note lowest lateral portion in direct contact with 166).
Moens does not disclose the use of a field plate dielectric spacer within the field plate opening in the ILDO such that the field plate dielectric spacer includes a horizontal dielectric spacer portion that contacts the upper surface of the surface passivation. However the use of dielectric spacers with field plates is well known in the art. Puglisi discloses the use of dielectric spacers (26A, 26B, 36A, 36B, 46A, 46B) in fig. 1D, 2I, 3J, and 4E. Puglisi states that the dielectric spacers allows the field plate to have a gradual shape which spreads the electric field (p. 6, paragraph 142, p. 8, paragraph 205). Xia discloses that spreading the electric field between the gate and the drain improves the breakdown voltage of the device (p. 6, paragraph 69). In view of Puglisi and Xia, it would therefore be obvious to implement a dielectric spacer within the field plate opening in the first interlayer dielectric (720) such that the dielectric spacer includes a horizontal dielectric spacer portion that contacts the upper surface of the surface passivation (164, 166) in the Moens device. In the device of Moens constructed in view of Puglisi and Xia, the first field plate (1457 – note lowest lateral portion in direct contact with 166) within the field plate opening in the first interlayer dielectric (720) contacts the field plate dielectric spacer.
With regard to claim 2, in the device of Moens constructed in view of Puglisi and Xi, the second field plate (fig. 14A of Moens: 1457 – note highest lateral portion in direct contact with 720) with a fourth horizontal bottom extent overlies and contacts an upper surface of the horizontal dielectric spacer portion.
In reference to claim 9, Moens discloses that the surface passivation (164, 166) can include fewer films (column 6, lines 22-43). Thus in fig. 14A of Moens, the surface passivation (166) consists of a single surface passivation layer (166) formed on the upper surface of the semiconductor substrate (102, 106, 122). An upper surface of the single surface passivation layer (166) defines the upper surface of the surface passivation (166). The third horizontal bottom extent of the first field plate (1457 – note lowest lateral portion in direct contact with 166) contacts the upper surface of the single surface passivation layer (166).
With regard to claim 10, Moens discloses that the single surface passivation layer (166) is made of silicon nitride (column 6, lines 38-40).
In reference to claim 11, the surface passivation (164, 166) of Moens includes a lower surface passivation sub-layer (164) formed on the upper surface of the semiconductor substrate (102, 106, 122) and an upper surface passivation sub-layer (166) formed on the lower surface passivation sub-layer (164). An upper surface of the upper surface passivation sub-layer (166) defines the upper surface of the surface passivation (164, 166). The third horizontal bottom extent of the first field plate (1457 – note lowest lateral portion in direct contact with 166) contacts the upper surface of the upper surface passivation sub-layer (166).
With regard to claim 13, in fig. 14A of Moens, the first field plate (1457 – note lowest lateral portion in direct contact with 166) and the second field plate (1457 – note highest lateral portion in direct contact with 720) are formed from a field plate metal (column 7, lines 39-41). The semiconductor device further comprises a source metallization (1422) that extends from the field plate metal (1457) over the gate electrode (1426) to a source contact (722).
In reference to claim 14, the field plate metal (1457) includes titanium, platinum, gold, and nickel (column 7, lines 39-41). Moens discloses (column 8, lines 45-47) that the source metallization (1422) includes copper.
In reference to claim 15, in fig. 14A of Moens, the first field plate (1457 – note lowest lateral portion in direct contact with 166) and the second field plate (1457 – note highest lateral portion in direct contact with 720) are formed from a field plate metal (column 7, lines 39-41). A source metallization (1422) is connected to the field plate metal (208, 213) and extends over the gate electrode (1426) to a source contact (205). Moens discloses (column 8, lines 45-47) that the source metallization (1422) includes copper.
Moens does not disclose that the first field plate (1457 – note lowest lateral portion in direct contact with 166), the second field plate (1457 – note highest lateral portion in direct contact with 720), and the source metallization (1422) are one single continuous metallization layer. The examiner would like to note that such an issue (i.e., the integration of multiple pieces into one piece or conversely, using multiple pieces in replacing a single piece) has been previously decided by the courts:
In Howard v. Detroit Stove Works, 150 U.S. 164 (1893), the Court held, "it involves no invention to cast in one piece an article which has formerly been cast in two pieces and put together...."
Also in In re Larson, 144 USPQ 347 (CCPA 1965), the term "integral" did not define over a multi-piece structure secured as a single unit. More importantly, the court went further and stated, "we are inclined to agree with the solicitor that the use of a one-piece construction instead of the [multi-piece] structure disclosed in Tuttle et al. would be merely a matter of obvious engineering choice" (bracketed material added). The court cited In re Fridolph for support.
In re Fridolph, 135 USPQ 319 (CCPA 1962), deals with submitted affidavits relating to this issue. The underlying issue in In re Fridolph was related to the end result of making a multi-piece structure into a one-piece structure. Generally, favorable patentable weight was accorded if the one-piece structure yielded results not expected from the modification of the two-piece structure into a single piece structure.
Therefore, it would have been obvious to one of ordinary skill in the art to integrally form the first field plate (1457 – note lowest lateral portion in direct contact with 166), the second field plate (1457 – note highest lateral portion in direct contact with 720), and the source metallization (1422) as one single continuous metallization layer since it is "merely a matter of obvious engineering choice" as set forth in the above case law.
In reference to claim 16, Moens discloses a similar method. Fig. 14A of Moens discloses a method of fabricating a semiconductor device which comprises a providing a semiconductor substrate (102, 106, 122) with an upper surface and a channel (122). A surface passivation (164, 166) is formed over the upper surface of the semiconductor substrate (102, 106, 122). A first interlayer dielectric (720) is formed over an upper surface of the surface passivation (164, 166). A field plate opening in the first interlayer dielectric (720) exposed a portion of the upper surface of the surface passivation (164, 166). Source (622) and drain (624) electrodes are formed over the upper surface of the semiconductor substrate (102, 106, 122). The source (622) and drain (624) electrodes are electrically coupled to the channel (122). The channel (122) extends between the source (622) and drain (624) electrodes. A gate electrode (1426) is formed over the upper surface of the semiconductor substrate (102, 106, 122) is between the source (622) and drain (624) electrodes. The gate electrode (1426) includes a gate channel portion that extends through the surface passivation (164, 166) to contact the upper surface of the semiconductor substrate (102, 106, 122), a first gate field plate (1426 – note lowest lateral portion in direct contact with 166) with a first horizontal bottom extent that overlies the upper surface of the surface passivation (164, 166), and a second gate field plate (1426 – note highest lateral portion in direct contact with 720) with a second horizontal bottom extent that is higher than the first horizontal bottom extent. A conductive field plate (208, 213) is formed over the upper surface of the semiconductor substrate (102, 106, 122) between the gate electrode (212) and the drain electrode (206). The conductive field plate (208, 213) includes a first field plate (208) with a third horizontal bottom extent that overlies and contacts the upper surface of the surface passivation (207). There is a second field plate (213) with a fourth horizontal bottom extent (213 – rightmost portion with bottom surface in direct contact with 209) that is at least as high as the first horizontal bottom extent of the first gate field plate (212 – note lowest lateral portion in direct contact with 209). A conductive plate (1457) is formed over the upper surface of the semiconductor substrate (102, 106, 122) and is between the gate electrode (1426) and the drain electrode (624). Moens does not describe the conductive material (1457) as a conductive field plate. However the examiner would like to note that the elements must be arranged as required by the claim, but this is not an ipsissimis verbis test, i.e., identity of terminology is not required. See In re Bond, 910 F.2d 831, 15 USPQ2d 1566 (Fed. Cir. 1990). Although Moens does not specifically use the term, “conductive field plate,” it is not required in order for the Moens reference to teach this limitation in the claim. Thus this limitation is not patentable over Moens. The conductive field plate (1457) includes a first field plate (1457 – note lowest lateral portion in direct contact with 166) within the field plate opening in the first interlayer dielectric (720) with a third horizontal bottom extent that overlies and contacts the upper surface of the surface passivation (164, 166). There is a second field plate (1457 – note highest lateral portion in direct contact with 720) with a fourth horizontal bottom extent that is at least as high as the first horizontal bottom extent of the first gate field plate 1426 – note lowest lateral portion in direct contact with 166).
Moens does not disclose the use of a first field plate dielectric spacer within the field plate opening in the ILDO such that the field plate dielectric spacer includes a horizontal dielectric spacer portion that contacts the upper surface of the surface passivation. However the use of dielectric spacers with field plates is well known in the art. Puglisi discloses the use of dielectric spacers (26A, 26B, 36A, 36B, 46A, 46B) in fig. 1D, 2I, 3J, and 4E. Puglisi states that the dielectric spacers allows the field plate to have a gradual shape which spreads the electric field (p. 6, paragraph 142, p. 8, paragraph 205). Xia discloses that spreading the electric field between the gate and the drain improves the breakdown voltage of the device (p. 6, paragraph 69). In view of Puglisi and Xia, it would therefore be obvious to implement a dielectric spacer within the field plate opening in the first interlayer dielectric (720) such that the dielectric spacer includes a horizontal dielectric spacer portion that contacts the upper surface of the surface passivation (164, 166) in the Moens method. In the method of Moens constructed in view of Puglisi and Xia, the first field plate (1457 – note lowest lateral portion in direct contact with 166) within the field plate opening in the first interlayer dielectric (720) contacts the first field plate dielectric spacer.
With regard to claim 23, Moens discloses that the surface passivation (164, 166) can include fewer films (column 6, lines 22-43). Thus in fig. 14A of Moens, the surface passivation (166) consists of a single surface passivation layer (166) formed on the upper surface of the semiconductor substrate (102, 106, 122). An upper surface of the single surface passivation layer (166) defines the upper surface of the surface passivation (166).
In reference to claim 24, forming the surface passivation (164, 166) of Moens comprises forming a lower surface passivation sub-layer (164) formed on the upper surface of the semiconductor substrate (102, 106, 122) and forming an upper surface passivation sub-layer (166) formed on the lower surface passivation sub-layer (164). An upper surface of the upper surface passivation sub-layer (166) defines the upper surface of the surface passivation (164, 166).
With regard to claim 25, in fig. 14A of Moens, forming the conductive field plate (1457) includes forming the first field plate (1457 – note lowest lateral portion in direct contact with 166) and the second field plate (1457 – note highest lateral portion in direct contact with 720) from a field plate metal (column 7, lines 39-41). The method further comprises forming a source metallization (1422) that extends from the field plate metal (1457) over the gate electrode (1426) to a source contact (722).
In reference to claim 26, in fig. 14A of Moens, the first field plate (1457 – note lowest lateral portion in direct contact with 166) and the second field plate (1457 – note highest lateral portion in direct contact with 720) are formed from a field plate metal (column 7, lines 39-41). A source metallization (1422) is connected to the field plate metal (208, 213) and extends over the gate electrode (1426) to a source contact (205).
Moens does not disclose that the first field plate (1457 – note lowest lateral portion in direct contact with 166), the second field plate (1457 – note highest lateral portion in direct contact with 720), and the source metallization (1422) are one single continuous metallization layer. The examiner would like to note that such an issue (i.e., the integration of multiple pieces into one piece or conversely, using multiple pieces in replacing a single piece) has been previously decided by the courts:
In Howard v. Detroit Stove Works, 150 U.S. 164 (1893), the Court held, "it involves no invention to cast in one piece an article which has formerly been cast in two pieces and put together...."
Also in In re Larson, 144 USPQ 347 (CCPA 1965), the term "integral" did not define over a multi-piece structure secured as a single unit. More importantly, the court went further and stated, "we are inclined to agree with the solicitor that the use of a one-piece construction instead of the [multi-piece] structure disclosed in Tuttle et al. would be merely a matter of obvious engineering choice" (bracketed material added). The court cited In re Fridolph for support.
In re Fridolph, 135 USPQ 319 (CCPA 1962), deals with submitted affidavits relating to this issue. The underlying issue in In re Fridolph was related to the end result of making a multi-piece structure into a one-piece structure. Generally, favorable patentable weight was accorded if the one-piece structure yielded results not expected from the modification of the two-piece structure into a single piece structure.
Therefore, it would have been obvious to one of ordinary skill in the art to integrally form the first field plate (1457 – note lowest lateral portion in direct contact with 166), the second field plate (1457 – note highest lateral portion in direct contact with 720), and the source metallization (1422) as one single continuous metallization layer since it is "merely a matter of obvious engineering choice" as set forth in the above case law.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Moens in view of Puglisi and further in view of Xia as applied to claim 11 above and further in view of Kajitani et al. (United States Patent Application Publication No. US 2015/0194483 A1, hereinafter “Kajitani”).
In reference to claim 12, Moens does not disclose that the lower surface passivation sub-layer (164) is formed from silicon nitride. Moens also does not disclose that the upper surface passivation sub-layer (166) is formed from aluminum oxide or aluminum nitride. However Kajitani discloses that aluminum oxide, aluminum nitride, and silicon nitride are known passivation layer materials (p. 4, paragraph 101, p. 4-5, paragraph 114). The applicant is reminded in this regard that it has been held that the selection of a known material based on its suitability for its intended use would be entirely obvious. See Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) ("Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.). See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960) (selection of a known plastic to make a container of a type made of plastics prior to the invention was held to be obvious). See MPEP 2144.07. In view of the above, it would therefore be obvious to implement an upper surface passivation layer made of silicon nitride and a lower surface passivation layer made of aluminum oxide or aluminum nitride.
Allowable Subject Matter
Claims 3 and 17-22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: in the examiner’s opinion, it would not be obvious to implement a semiconductor device which comprises a semiconductor substrate with an upper surface and a channel, source and drain electrodes over the upper surface of the semiconductor substrate such that the source and drain electrodes are electrically coupled to the channel which extends between the source and drain electrodes with a surface passivation and a first interlayer dielectric (ILD0) over the upper surface of the semiconductor substrate, a field plate dielectric spacer in a field plate opening in the first interlayer dielectric (ILD0), a gate electrode with a field plate structure with first and second gate field plates, a conductive field plate with first and second field plates in combination with the specific third field plate structure of the conductive field plate as described by the applicant in claim 3. In the examiner’s opinion, it would also not be obvious to implement a method of fabricating a semiconductor device which comprises providing a semiconductor substrate with an upper surface and a channel, forming a surface passivation and a first interlayer dielectric (ILD0) over the upper surface of the semiconductor substrate, forming source and drain electrodes over the upper surface of the semiconductor substrate such that the source and drain electrodes are electrically coupled to the channel which extends between the source and drain electrodes, forming a field plate dielectric spacer in a field plate opening in the first interlayer dielectric (ILD0), forming a gate electrode with a field plate structure with first and second gate field plates, forming a conductive field plate with first and second field plates, in combination with the specific steps of the field plate dielectric spacer formation, the gate dielectric spacer formation, the formation of the third plate of the conductive field plate, and the first interlayer dielectric structure formation as described by the applicant in claims 17, 18, 20, and 21.
Response to Arguments
Applicant’s arguments with respect to claims 1-26 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEVIN QUINTO whose telephone number is (571)272-1920. The examiner can normally be reached Monday-Friday, 9-5:30.
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/KEVIN QUINTO/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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