Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of group I in the reply filed on 02/10/26 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 and 13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bothe et al., US 2022/0130985.
Bothe et al. shows the invention as claimed including a semiconductor device comprising:
A semiconductor substrate 112 with an upper surface and a channel;
Source and drain electrodes (124,126) over the upper surface of the semiconductor substrate, wherein the source and drain electrodes are electrically coupled to the channel (for example, 116), and the channel extends between the source and drain electrodes;
Surface passivation 125 over the upper surface of the semiconductor substrate between the source and drain electrodes (124,126);
A first interlayer dielectric 121 over an upper surface of the surface passivation;
A gate electrode 122 over the upper surface of the semiconductor substrate between the source and drain electrodes (124,126), wherein the gate electrode includes a gate channel portion that extends through the surface passivation 125 to contact the upper surface of the semiconductor substrate 112, a first gate field plate 122 with a first horizontal bottom extent that overlies and contacts the upper surface of the surface passivation 125, and a second gate field plate with a second horizontal bottom extent that is higher than the first horizontal bottom extent (see portion that overlies layer 121); and a conductive field plate 140 over the upper surface of the semiconductor substrate between the gate electrode and the drain electrode, wherein the conductive field plate includes a first field plate with a third horizontal bottom extent that is recessed below the upper surface of the surface passivation 125, and a second field plate with a fourth horizontal bottom extent that is higher than the first horizontal bottom extent of the first gate field plate (see portion that rests on insulating layer 121, and for description of entire device see figs. 3-4D and paragraphs 0066-0102).
Concerning dependent claim 2, note that Fisher et al. discloses a horizontal dielectric spacer portion 164 on an upper surface of the surface passivation 125, wherein the fourth horizontal bottom extent of the second field plate overlies and contacts an upper surface of the horizontal dielectric spacer portion (see, for example, fig. 3).
Regarding dependent claim 13, note that Fisher et al. discloses wherein the first field plate and the second plate are formed from a field plate metal and the semiconductor device further comprises a source metallization that extends from the field plate metal over the gate electrode to a source contact (see fig. 5H and paragraphs 0059).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bothe et al., US 2022/0130985.
Bothe et al. additionally discloses the source metallization include one of the claimed materials such as copper and platinum, respectively (see paragraphs 0060) but fails to expressly disclose the field plate being made of one of the claimed materials. However, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to construct the field plate of similar materials as the source metallization because they are both contact materials and to use the same material would be more convenient and cost effective.
Claim(s) 3-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bothe et al., US 2022/0130985 in view of Chen et al., US 2021/0407947.
Bothe et al. is applied as above but does not expressly disclose the surface passivation includes a lower surface passivation sub-layer formed on the upper surface of the semiconductor substrate and being made of silicon nitride, an intermediate surface passivation sub-layer formed on the lower surface passivation sub-layer and being formed of silicon dioxide, and an upper surface passivation sub-layer 146C formed on the intermediate surface passivation sub-layer and defining an upper surface of the surface passivation and being made of one from the group selected from aluminum oxide, aluminum nitride, and hafnium oxide. Chen et al. discloses a lower surface passivation sub-layer 146A formed on the upper surface of the semiconductor substrate and being made of silicon nitride, an intermediate surface passivation sub-layer 146B formed on the lower surface passivation sub-layer and being formed of silicon dioxide, and an upper surface passivation sub-layer formed on the intermediate surface passivation sub-layer and defining an upper surface of the surface passivation and being made of one from the group selected from aluminum oxide, aluminum nitride, and hafnium oxide (see fig. 3A and paragraph 0028). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the primary reference of Bothe et al. so as to comprise the claimed passivation configuration as disclosed by Chen because in such a way an optimization of different physical and electrical properties can be achieved.
As to dependent claim 6, note that Bothe et al. does not expressly disclose wherein the third horizontal bottom extent of the first field plate contacts an upper surface of the lower surface passivation sub-layer. However, Chen teaches wherein the third horizontal bottom extent of the first field plate contacts an upper surface of the lower surface passivation sub-layer 146a (see figs. 1 and 3A and their descriptions). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the primary reference of Bothe et al. so as to comprise the claimed configuration of the third horizontal bottom of the first field plate because this is shown to be suitable configuration for an HEMT including a field plate structure.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bothe et al., US 2022/0130985 in view of Ho et al., U.S. Patent 11,335,784.
Bothe et al. is applied as above but fails to expressly disclose where the conductive field plate further includes a third field plate with a fifth horizontal bottom extent that is higher than the fourth horizontal bottom extent of the second field plate. Ho et al. discloses a conductive field plate that further includes a third field plate 312c with a fifth horizontal bottom extent that is higher than the fourth horizontal bottom extent of the second field plate 312b (see fig. 3A and its description). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the primary reference of Bothe et al. so as to comprise the claimed third field plate configuration because in such a way the device performance can be optimized.
Claim(s) 8-9 and 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bothe et al., US 2022/0130985 in view of Ho et al., U.S. Patent 11,335,784 as applied to claim 7 above, and further in view of Djemour et al., US 2022/0359314.
Bothe et al. and Ho et al. shows the invention substantially as claimed but fails to expressly disclose the claimed ILD0/field plate configuration. However, Djemour et al. discloses the ILD0 includes a lower ILD0 sub-layer on the upper surface of the surface passivation, and an intermediate ILD0 sub-layer on an upper surface of the lower ILD0 sub-layer (see, for example, paragraph 0041); the fifth horizontal bottom extent of the third field plate overlies and contacts the upper surface of the lower ILD0 sub-layer (see fig. 1B); and the second horizontal bottom extent of the second gate field plate overlies an upper surface of the intermediate ILD0 sub-layer (bottom portion of 350 penetrates through 210 to contact the intermediate sub-layer—see fig. 1B and its description). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the device of Bothe et al. modified by Ho et al. so as to comprise the claimed configuration as disclosed by Djemour et al. because this creates an optimal semiconductor device which high breakdown resistance.
Concerning claim 9, note that Bothe et al. and Ho et al. do not expressly disclose the claimed upper ILD0 layer and conducive field plate. However, Ho teaches an ILD0 that includes an upper ILD0 sub-layer 126 (see fig. 3A and its description). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the primary reference of Fisher et al. to include the claimed upper ILD0 layer because this creates an optimal semiconductor device which high breakdown resistance. With respect to the claimed conductive field plate, official notice is taken that it would have been obvious to one ordinary skill in the art at the time the invention was filed to comprise the claimed staircase configuration because such a configuration is well known in the formation of electrodes particularly in HEMT devices because of the desirable electrical characteristics that they produce.
With respect to dependent claim 11, Bothe additionally discloses a first gate field plate and the second gate field plate project upwardly and outwardly from the gate channel portion (see fig. 5H) but does not expressly disclose the second field plate and the third field plate project upwardly and outwardly from the first field plate. However, Ho et al. discloses the second field plate 312b and the third field plate 312c project upwardly and outwardly from the first field plate (see fig. 3A and its description). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the primary reference of Bothe et al. so as to comprise the claimed field plate configuration because this creates a staircase or stepped configuration that is a well known structure common in field plates.
Concerning dependent claim 12, Fisher et al. does not expressly disclose the first gate field plate and the second gate field plate are located on a drain side of the gate electrode; the gate electrode further includes another first gate field plate and another second gate field plate located on a source side of the gate electrode, the second field plate and the third field plate are located on a gate side of the conductive field plate; and the conductive field plate further includes another second field plate and another third field plate on a drain side of the conductive field plate. However, Ho discloses the first gate field plate (108 in layer 310a) and the second gate field plate (108 in layer 132b) are located on a drain side 106 of the gate electrode 108; the gate electrode further includes another first gate field plate 314 layer 312a) and another second gate field plate (314 layer 312b) located on a source side 308 of the gate electrode, the second field plate (122 layer 312b) and the third field plate (122 layer 312c) are located on a gate side of the conductive field plate 122; and the conductive field plate further includes another second field plate 122 layer 312b) and another third field plate (122 layer 312c) on a drain side of the conductive field plate (see fig. 3a and its description). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the device of Bothe et al. so as to comprise the field plate configuration as claimed and disclosed by Ho et al. because this allows for an optimized device with high voltage capability.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bothe et al., US 2022/0130985 in view of Ho et al., U.S. Patent 11,335,784 and Djemour et al., US 2022/0359314 as applied to claims 8-9 and 11-12 above, and further in view of Huang et al., US Patent 12,040,273.
Bothe et al., Ho et al., and Djemour et al. are applied as above but do not expressly disclose the lower ILD0 formed from silicon nitride, the intermediate ILD0 formed from silicon dioxide, and the upper ILD layer is formed from silicon nitride. Huang et al. discloses the lower ILD0 formed from silicon nitride, the intermediate ILD0 formed from silicon dioxide, and the upper ILD layer is formed from silicon nitride (see col. 8-line 18 to col. 12-line 34). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the device of Bothe et al. modified by Ho et al. and Djemour et al. so as to comprise interlevel dielectric layers formed of the claimed materials as disclosed by Huang et al. because these are shown to be suitable insulative materials for interlayers.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 and 3-14 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-6 and 8-14 of copending Application No. 18/499100. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant application are broader than the claims of the ‘100 application because they do not include the limitation of “a field pate dielectric spacer on the upper surface of the surface passivation between the third horizontal bottom extent of the first field plate and the fourth horizontal bottom extent of the second field plate”. However, under a one way obviousness type double patenting test, a prima facie case of obviousness type double patenting has been established.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim 2 is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-6 and 8-14 of copending Application No. 18/499100 in view of Bothe et al., US 2022/0130985.
Claims 1-6 and 8-14 of the ‘100 application are applied as above but do not expressly disclose a horizontal dielectric spacer portion on an upper surface of the surface passivation, wherein the fourth horizontal bottom extent of the second field plate overlies and contacts an upper surface of the horizontal dielectric spacer portion.
Bothe et al. discloses a horizontal dielectric spacer portion 164 on an upper surface of the surface passivation 125, wherein the fourth horizontal bottom extent of the second field plate overlies and contacts an upper surface of the horizontal dielectric spacer portion (see, for example, fig. 3). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the primary reference represented by claims 1-6 and 8-14 of application 18/499100 so as to form the claimed horizontal dielectric spacer portion because in such a way the field plate will be adequately spaced from the passivation layer and problems such as short-circuiting will be less likely to occur.
This is a provisional nonstatutory double patenting rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD A BOOTH whose telephone number is (571)272-1668. The examiner can normally be reached Monday to Friday, 8:30 to 5:00.
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/RICHARD A BOOTH/Primary Examiner, Art Unit 2812
February 28, 2026