DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/01/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 15 and 22 are rejected under 35 U.S.C. 102 as being anticipated by Fisher et al. US 2024/0162304 A1; hereinafter Fisher
Regarding claim 15, Fisher teaches a method of fabricating a semiconductor device, the method comprising: providing a semiconductor substrate ( Fig. 5H #112, #116, and #118 ) with an upper surface ( Fig. 5H #118 ) and a channel ( Fig. 5H #116 ) ; forming surface passivation ( Fig. 5H #125 ) over the upper surface of the semiconductor substrate ( Fig. 5H #118 ); forming a first interlayer dielectric (ILD0) over an upper surface of the surface passivation ( Fig. 5H #121 ) ; forming source ( Fig. 5H #126 ) and drain electrodes ( Fig. 5H #124 ) over the upper surface of the semiconductor substrate ( Fig. 5H #122 ), wherein the source ( Fig. 5H #126 ) and drain electrodes ( Fig. 5H #122D ) are electrically coupled to the channel ( [0075] The 2DEG layer acts as a highly conductive layer that allows conduction between the source and drain regions of the device that are beneath the source contact #126 the drain contact #124, respectively ) , and the channel extends between the source and drain electrodes ( as discussed above ); forming a gate electrode ( Fig. 5H #122 ) over the upper surface of the semiconductor substrate ( Fig. 5H #118 ) between the source ( Fig. 5H #126 ) and drain electrodes ( Fig. 5H #124 ), wherein the gate electrode ( Fig. 5H #122 ) includes a gate channel portion ( Fig. 5H #122D ) that extends through the surface passivation ( Fig. 5H #125 ) to contact the upper surface of the semiconductor substrate ( Fig. 5H #118 ), a first gate field plate ( Fig. 5H field plate #140 ) with a first horizontal bottom extent that overlies and contacts the upper surface of the surface passivation ( Fig. 5H #121 ), and a second gate field plate ( Fig. 5H #125 ) with a second horizontal bottom extent that is higher than the first horizontal bottom extent ( as shown in Fig. 5H ); and forming a conductive field plate ( Fig. 5H #123 ) over the upper surface of the semiconductor substrate ( Fig. 5H #112 ) between the gate electrode ( Fig. 5H #122 ) and the drain electrode ( Fig. 5H #124 ), wherein the conductive field plate ( Fig. 5H #123 ) includes a first field plate with a third horizontal bottom extent that is recessed below the upper surface of the surface passivation ( bottom portion of #123 is recessed below the passivation #121) , and a second field plate with a fourth horizontal bottom extent that is higher than the first horizontal bottom extent of the first gate field plate ( top portion of #123 that rests on #121 ).
Regarding claim 22, Fisher teaches the method of claim 15 ( as discussed above), wherein: forming the conductive field plate includes forming the first field plate ( upper section of #123 ) and the second field plate ( lower section of #123 ) from a field plate metal ( [0100] The metal contacts #123, #125 may contain metal or other highly conductive material, including, for example, copper, cobalt, gold, and/or a composite metal ); and the method further comprises forming a source metallization that extends from the field plate metal over the gate electrode to a source contact ( [0033] the field plate includes a source-side wing portion extending from a central portion of the field plate ).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1, 13, and 14 are rejected under U.S.C. 103 as being unpatentable over Fisher et al. US 2024/0162304 A1; ( CON of application filed 10/2020) in view of Sel et al.; US 10319680 B1; 03/2018
Claim 1: Fisher discloses a semiconductor device comprising: a semiconductor substrate ( Fig. 5H host substrate #112, channel layer #116, and barrier layer #118 ) with an upper surface ( as shown in Fig. 5H ) and a channel ( Fig. 5H channel layer #116 ) ; source ( Fig. 5H source contact #126 ) and drain electrodes ( Fig. 5H drain contact #124 ) over the upper surface ( as shown in Fig. 5H ) of the semiconductor substrate ( Fig. 5H #112 ), wherein the source ( Fig. 5H #126 ) and drain electrodes ( Fig. 5H #124 ) are electrically coupled to the channel ( Fig. 5H barrier layer #118 contacts #126 and #124 which is on top of #116 so the channel layer is electrically coupled to the source and drain contacts ), and the channel extends between the source and drain electrodes ( as shown in Fig. 5H ); surface passivation ( Fig. 5H passivation layer #125 ) over the upper surface of the semiconductor substrate ( Fig. 5H #118 ) between the source ( Fig. 5H #126 ) and drain electrodes ( Fig. 5H #124 ); a first interlayer dielectric (ILD0) over an upper surface of the surface passivation [0087] The first insulating layer #125 and the second insulating layer #121 may serve as passivation layers for the HEMT device #100 and may also act as insulating interlayers ); a gate electrode ( Fig. 5H gate contact #122 ) over the upper surface of the semiconductor substrate ( Fig. 5H #112 ) between the source ( Fig. 5H #126 ) and drain electrodes ( Fig. 5H #124 ), wherein the gate electrode ( Fig. 5H #122 ) includes a gate channel portion that extends through the surface passivation to contact the upper surface of the semiconductor substrate ( as shown in Fig. 5H #122 penetrates #125 to contact the upper surface of the semiconductor substrate ), a first gate field plate ( Fig. 5H field plate #140 ) with a first horizontal bottom extent that overlies and contacts the upper surface of the surface passivation ( Fig. 5H #121 ), and a second gate field plate ( Fig. 5H #125 ) with a second horizontal bottom extent that is higher than the first horizontal bottom extent ( as shown in Fig. 5H ); a conductive field plate ( Fig. 5H #123 ) over the upper surface of the semiconductor substrate ( Fig. 5H #112 ) between the gate electrode ( Fig. 5H #122 ) and the drain electrode ( Fig. 5H #124 ), wherein the conductive field plate ( Fig. 5H #123 ) includes a first field plate with a third horizontal bottom extent that is recessed below the upper surface of the surface passivation ( bottom portion of #123 is recessed below the passivation #121) , and a second field plate with a fourth horizontal bottom extent that is higher than the first horizontal bottom extent of the first gate field plate ( top portion of #123 that rests on #121 ).
Fisher does not appear to disclose a field plate dielectric spacer on the upper surface of the surface passivation between the third horizontal bottom extent of the first field plate and the fourth horizontal bottom extent of the second field plate.
However, Sel teaches a field plate dielectric spacer ( Fig. 1 dielectric spacer #756 ) on the upper surface of the surface passivation ( Fig. 1 #720 ) between the third horizontal bottom extent of the first field plate ( Fig. 1 #758 ) and the fourth horizontal bottom extent of the second field plate ( Fig. 1 #754 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Fisher with Sel to implement a field plate dielectric spacer on the upper surface of the surface passivation between the third horizontal bottom extent of the first field plate and the fourth horizontal bottom extent of the second field plate because the spacer helps to further spread out and disperse the electric field across the channel.
Claim 13: Fisher and Sel disclose the semiconductor device of claim 1 ( as discussed above ).
Fisher teaches the first field plate ( Fig. 5H upper section of #123 ) and the second field plate ( Fig. 5H lower section of #123 ) are formed from a field plate metal ( [0100] The metal contacts #123, #125 may contain metal or other highly conductive material, including, for example, copper, cobalt, gold, and/or a composite metal ); and the semiconductor device further comprises a source metallization that extends from the field plate metal over the gate electrode to a source contact ( [0033] the field plate includes a source-side wing portion extending from a central portion of the field plate ).
Claim 14: Fisher and Sel disclose the semiconductor device of claim 13 ( as discussed above).
Fisher teaches the field plate metal includes one or more materials selected from titanium, titanium tungsten, titanium aluminum, titanium tungsten nitride, gold, aluminum, molybdenum, nickel, polysilicon, platinum, copper, and tantalum; and the source metallization includes one or more materials selected from titanium, titanium tungsten, titanium aluminum, titanium tungsten nitride, gold, titanium-aluminum-gold, aluminum, molybdenum, nickel, polysilicon, germanium, platinum, copper, and tantalum ( [0100] The metal contacts #123, #125 may contain metal or other highly conductive material, including, for example, copper, cobalt, gold, and/or a composite metal ).
Claim 2-5 are rejected under U.S.C. 103 as being unpatentable over Fisher et al. US 2024/0162304 A1; ( CON of application filed 10/2020) in view of Sel et al.; US 10319680 B1; 03/2018 as it applies to claim 1 and further in view of Chen et al.; US 2021/0407947 A1; 06/2020
Claim 2: Fisher and Sel disclose the semiconductor device of claim 1 ( as discussed above).
Neither Fisher nor Sel appear to disclose the surface passivation includes a lower surface passivation sub-layer formed on the upper surface of the semiconductor substrate, an intermediate surface passivation sub-layer formed on the lower surface passivation sub-layer, and an upper surface passivation sub-layer formed on the intermediate surface passivation sub-layer and defining an upper surface of the surface passivation.
However, Chen teaches the surface passivation ( Fig. 3A #146 ) includes a lower surface passivation sub-layer ( Fig. 3A #146 A ) formed on the upper surface of the semiconductor substrate ( Fig. 1 #140 is on the upper surface of the substrate ), an intermediate surface passivation sub-layer ( Fig. 3A #146B ) formed on the lower surface passivation sub-layer ( Fig. 3A #146A ), and an upper surface passivation sub-layer ( Fig. 3A #146C ) formed on the intermediate surface passivation sub-layer ( Fig. 3A #146B ) and defining an upper surface of the surface passivation ( as shown in Fig. 3A ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Chen with Fisher and Sel to implement the surface passivation includes a lower surface passivation sub-layer formed on the upper surface of the semiconductor substrate, an intermediate surface passivation sub-layer formed on the lower surface passivation sub-layer, and an upper surface passivation sub-layer formed on the intermediate surface passivation sub-layer and defining an upper surface of the surface passivation because a three-part surface passivation scheme is implemented to provide a specialized, multi-functional barrier that balances interface quality, structural integrity, and environmental protection.
Claim 3: Fisher, Sel, and Chen disclose the semiconductor device of claim 2 ( as discussed above).
Neither Fisher nor Sel appear to disclose the lower surface passivation sub-layer is formed from silicon nitride; the intermediate surface passivation sub-layer is formed from silicon dioxide; and the upper surface passivation sub-layer is formed from a material selected from aluminum oxide, aluminum nitride, and hafnium oxide.
However, Chen teaches the lower surface passivation sub-layer ( Fig. 3A #146A ) is formed from silicon nitride ( [0028] Each of the first passivation sublayer 146A, second passivation sublayer 146B, and third passivation sublayer 146C is made from a dielectric material, such as silicon oxide, silicon oxycarbide, one or more porous low-k dielectric materials, undoped silica glass, borophosphosilicate glass, phosphosilicate glass, boron silicate glass, silicon nitride, silicon oxynitride, silicon oxycarbon nitride, high density plasma oxide formed by HDP-CVD process or other suitable processes, spin on glass, polyimide, other suitable materials, or a combination thereof ); the intermediate surface passivation sub-layer ( Fig. 3A #146B ) is formed from silicon dioxide ( silicon dioxide is a dielectric material so would be in the list described above ); and the upper surface passivation sub-layer is formed from a material selected from aluminum oxide, aluminum nitride, and hafnium oxide ( [0028] At least one of the first, second, and third passivation sublayers 146A, 146B, 146C is made from a nitride, such as silicon nitride, aluminum nitride, titanium nitride, or tantalum nitride ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Chen with Fisher and Sel to implement the lower surface passivation sub-layer is formed from silicon nitride; the intermediate surface passivation sub-layer is formed from silicon dioxide; and the upper surface passivation sub-layer is formed from a material selected from aluminum oxide, aluminum nitride, and hafnium oxide because the three-part passivation stack is implemented to optimize the balance between interface quality, electrical field management, and environmental protection.
Claim 4: Fisher, Sel and Chen disclose the semiconductor device of claim 2 ( as discussed above).
Fisher discloses the third horizontal bottom extent of the first field plate ( bottom portion of #123 is recessed below the passivation #121 )
Neither Fisher nor Sel appear to disclose contacts an upper surface of the intermediate surface passivation sub-layer.
However, Chen teaches contacts an upper surface of the intermediate surface passivation sub-layer ( Fig. 3A #146B; Fig. 1 shows how the plate penetrates the #146 layer ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Chen with Fisher and Sel to implement contacts an upper surface of the intermediate surface passivation sub-layer because this allows for capacitance management, protection of the interface layer, and precision in electric field reduction.
Claim 5: Fisher, Sel and Chen disclose the semiconductor device of claim 2 ( as discussed above ).
Fisher discloses the third horizontal bottom extent of the first field plate ( bottom portion of #123 is recessed below the passivation #121 )
Neither Fisher nor Sel appear to disclose contacts an upper surface of the lower surface passivation sub-layer.
However, Chen teaches contacts an upper surface of the lower surface passivation sub-layer ( Fig. 3A #146A; Fig. 1 shows how the plate penetrates the #146 layer ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Chen with Fisher and Sel to implement contacts an upper surface of the lower surface passivation sub-layer because this would optimize electrical field management and heat dissipation within high-power or high-frequency transistors.
Claim 6 is rejected under U.S.C. 103 as being unpatentable over Fisher et al. US 2024/0162304 A1; ( CON of application filed 10/2020) in view of Sel et al.; US 10319680 B1; 03/2018 as it applies to claim 1 and further in view of Djemour et al.; US 2022/0359314 A1; 05/2022
Claim 6: Fisher and Sel disclose the semiconductor device of claim 1 ( as discussed above).
Neither Fisher nor Sel appear to disclose the ILD0 includes a lower ILD0 sub-layer on the upper surface of the surface passivation, and an intermediate ILD0 sub-layer on an upper surface of the lower ILD0 sub-layer; the fourth horizontal bottom extent of the second field plate overlies and contacts the upper surface of the lower ILD0 sub-layer; and the second horizontal bottom extent of the second gate field plate overlies an upper surface of the intermediate ILD0 sub-layer.
However, Djemour teaches the ILD0 includes a lower ILD0 sub-layer ( [0102] The interlayer dielectric #210 may include one single homogeneous layer or may include two or more sub-layers of different composition and/or different density or stoichiometry ) on the upper surface of the surface passivation ( [0041] an interlayer dielectric may be formed between the first surface and the passivation layer ), and an intermediate ILD0 sub-layer on an upper surface of the lower ILD0 sub-layer ( as discussed above ); the fourth horizontal bottom extent of the second field plate overlies and contacts the upper surface of the lower ILD0 sub-layer ( Fig. 1B #350 horizontal bottom contacts the upper surface of #210 ) ; and the second horizontal bottom extent of the second gate field plate overlies an upper surface of the intermediate ILD0 sub-layer ( Fig. 1B shows the bottom portion of #350 penetrates through #210 so it contacts the intermediate sub-layer ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Djemour with Fisher and Sel to implement the ILD0 includes a lower ILD0 sub-layer on the upper surface of the surface passivation, and an intermediate ILD0 sub-layer on an upper surface of the lower ILD0 sub-layer; the fourth horizontal bottom extent of the second field plate overlies and contacts the upper surface of the lower ILD0 sub-layer; and the second horizontal bottom extent of the second gate field plate overlies an upper surface of the intermediate ILD0 sub-layer because this creates a stepped vertical profile which smooths the electric field distribution across the gate-to-drain region preventing high-field peaks that lead to premature breakdown.
Claim 7 is rejected under U.S.C. 103 as being unpatentable over Fisher et al. US 2024/0162304 A1; ( CON of application filed 10/2020) in view of Sel et al.; US 10319680 B1; and Djemour et al.; US 2022/0359314 A1; 05/2022 as it applies to claim 6 and further in view of Yu et al.; US 9673213 B1; 02/2016
Claim 7: Fisher, Sel, and Djemour disclose the semiconductor device of claim 6 ( as discussed above).
Neither Fisher nor Sel nor Djemour appear to disclose the field plate dielectric spacer has an outer surface that extends from the upper surface of the surface passivation to an upper surface of the lower ILD0 sub-layer.
However, Yu teaches the field plate dielectric spacer ( Fig. 1 gate spacer #156 ) has an outer surface that extends from the upper surface of the surface passivation ( Fig. 1 #161 ) to an upper surface of the lower ILD0 sub-layer ( Fig. 1 #170 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Yu with Fisher, Sel, and Djemour to implement the field plate dielectric spacer has an outer surface that extends from the upper surface of the surface passivation to an upper surface of the lower ILD0 sub-layer because this allows for electric field management (field shaping)
Claim 8, 9, 11, and 12 are rejected under U.S.C. 103 as being unpatentable over Fisher et al. US 2024/0162304 A1; ( CON of application filed 10/2020) in view of Sel et al.; US 10319680 B1; 03/2018 as it applies to claim 1 and further in view of Ho et al.; US 11,335,784 B2; 11/2020
Claim 8: Fisher and Sel disclose the semiconductor device of claim 1 ( as discussed above).
Neither Fisher nor Sel appear to disclose the conductive field plate further includes a third field plate with a fifth horizontal bottom extent that is higher than the fourth horizontal bottom extent of the second field plate.
However, Ho teaches the conductive field plate ( Fig. 3A #122 ) further includes a third field plate ( Fig. 3A #312c ) with a fifth horizontal bottom extent that is higher than the fourth horizontal bottom extent ( as shown in Fig. 3A) of the second field plate ( Fig. 3A #312b ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Ho with Fisher, and Sel to implement the conductive field plate further includes a third field plate with a fifth horizontal bottom extent that is higher than the fourth horizontal bottom extent of the second field plate because this is a design technique to further manage the electric field and optimize device performance.
Claim 9: Fisher, Sel, and Ho disclose the semiconductor device of claim 8 ( as discussed above).
Neither Fisher nor Sel appear to disclose the ILD0 further includes an upper ILD0 sub-layer on the upper surface of the intermediate ILD0 sub-layer; and the third field plate overlies and contacts an upper surface of the upper ILD0 sub-layer.
However, Ho teaches the ILD0 further includes an upper ILD0 sub-layer ( Fig. 3A #126 ) on the upper surface of the intermediate ILD0 sub-layer (Fig. 3A #118 ); and the third field plate ( Fig. 3A #312c ) overlies and contacts an upper surface of the upper ILD0 sub-layer ( Fig. 3A shows the pillar contacts #312c and extends through #126 to the upper surface).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Ho with Fisher, and Sel to implement the ILD0 further includes an upper ILD0 sub-layer on the upper surface of the intermediate ILD0 sub-layer; and the third field plate overlies and contacts an upper surface of the upper ILD0 sub-layer because this is a sophisticated architectural choice aimed at maximizing device efficiency and longevity.
Claim 11: Fisher, Sel, and Ho disclose the semiconductor device of claim 8 ( as discussed above).
Fisher teaches the first gate field plate ( Fig. 5H #140 ) and the second gate field plate ( Fig. 5H #125 ) project upwardly and outwardly from the gate channel portion ( as shown in Fig. 5H ).
Fisher does not appear to disclose the second field plate and the third field plate project upwardly and outwardly from the first field plate.
However, Ho teaches the second field plate ( Fig. 3A #312b ) and the third field plate ( Fig. 3A #312c ) project upwardly and outwardly from the first field plate ( Fig. 3A #312a ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Ho with Fisher, and Sel to implement the second field plate and the third field plate project upwardly and outwardly from the first field plate because this creates a specific geometric configuration known as a staircase or stepped field plate structure.
Claim 12: Fisher, Sel, and Ho disclose the semiconductor device of claim 11 ( as discussed above).
Neither Fisher nor Sel appear to disclose the first gate field plate and the second gate field plate are located on a drain side of the gate electrode; the gate electrode further includes another first gate field plate and another second gate field plate located on a source side of the gate electrode; the second field plate and the third field plate are located on a gate side of the conductive field plate; and the conductive field plate further includes another second field plate and another third field plate on a drain side of the conductive field plate.
However, Ho teaches the first gate field plate ( Fig. 3A #108 in the middle of the figure layer #310a ) and the second gate field plate ( Fig. 3A #108 in the middle of layer #132b ) are located on a drain side ( Fig. 3A #106 ) of the gate electrode ( Fig. 3A #108 ); the gate electrode ( Fig. 3A #108 ) further includes another first gate field plate ( Fig. 3A #314 layer #312a ) and another second gate field plate ( Fig. 3A #314 layer #312b ) located on a source side ( Fig. 3A #308 ) of the gate electrode ( Fig. 3A #108 ); the second field plate ( Fig. 3A #122 layer #312b ) and the third field plate ( Fig. 3A #122 layer #312c ) are located on a gate side ( Fig. 3A #108 on the left side of the figure ) of the conductive field plate ( Fig. 3A #122 ); and the conductive field plate further includes another second field plate ( Fig. 3A #122 layer #312b ) and another third field plate ( Fig. 3A #122 layer #312 c ) on a drain side of the conductive field plate ( Fig. 3A right side of #122 on the side of #106 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Ho with Fisher, and Sel to implement the first gate field plate and the second gate field plate are located on a drain side of the gate electrode; the gate electrode further includes another first gate field plate and another second gate field plate located on a source side of the gate electrode; the second field plate and the third field plate are located on a gate side of the conductive field plate; and the conductive field plate further includes another second field plate and another third field plate on a drain side of the conductive field plate because this allows for bidirectional high-voltage capability with source and drain symmetry.
Claim 10 is rejected under U.S.C. 103 as being unpatentable over Fisher et al. US 2024/0162304 A1; ( CON of application filed 10/2020) in view of Sel et al.; US 10319680 B1; 03/2018 and Ho et al.; US 11,335,784 B2; 11/2020 as it applies to claim 9 and further in view of Huang et al.; US 12,040,273 B2; 10/2022
Claim 10: Fisher, Sel and Ho disclose the semiconductor device of claim 9 ( as discussed above).
Neither Fisher nor Sel nor Ho appear to disclose the lower ILD0 sub-layer is formed from a material selected from silicon nitride; the intermediate ILD0 sub-layer is formed from a material selected from silicon dioxide; and the upper ILD0 sub-layer is formed from a material selected from silicon nitride.
However, Huang teaches the lower ILD0 sub-layer ( Fig. 1 ILD_L ) is formed from a material selected from silicon nitride ( Col. 8 lines 18 – 21 In some embodiments, first ILD layer 270 includes SiO, SiON, TEOS formed oxide, PSG, BPSG, low-k dielectric material (K<3.9), other suitable dielectric material, or combinations thereof ) ; the intermediate ILD0 sub-layer ( Fig. 1 ILD_M ) is formed from a material selected from silicon dioxide ( Col. 10 lines 53 – 57 Second ILD layer 272 includes any suitable material, for example, SiC, LaO, AlO, AlON, ZrO, HfO, SiN, Si, ZnO, ZrN, ZrAlO, TiO, TaO, YO, TaCN, ZrSi, SiOCN, SiOC, SiCN, HfSi, LaO, SiO, other suitable material, or combinations thereof); and the upper ILD0 sub-layer ( Fig. 1 ILD_U ) is formed from a material selected from silicon nitride ( Col. 12 lines 30 – 34 Third ILD layer 274 includes any suitable material, for example, SiC, LaO, AlO, AlON, ZrO, HfO, SiN, Si, ZnO, ZrN, ZrAlO, TiO, TaO, YO, TaCN, ZrSi, SiOCN, SiOC, SiCN, HfSi, LaO, SiO, other suitable material, or combinations thereof ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Huang with Fisher, Sel, and Ho to implement the lower ILD0 sub-layer is formed from a material selected from silicon nitride; the intermediate ILD0 sub-layer is formed from a material selected from silicon dioxide; and the upper ILD0 sub-layer is formed from a material selected from silicon nitride because silicon nitride is a significantly better diffusion barrier than silicon dioxide against water molecules. Silicon dioxide is chosen for the thicker intermediate layer because it provides excellent electrical and thermal insulation.
Claim 16 is rejected under U.S.C. 103 as being unpatentable over Fisher et al. US 2024/0162304 A1; ( CON of application filed 10/2020) in view of Chen et al.; US 2021/0407947 A1; 06/2020
Claim 16: Fisher discloses the method of claim 15 ( as discussed above).
Fisher does not appear to disclose forming the surface passivation includes forming a lower surface passivation sub-layer on the upper surface of the semiconductor substrate, forming an intermediate surface passivation sub-layer on the lower surface passivation sub-layer, and forming an upper surface passivation sub-layer on the intermediate surface passivation sub-layer, wherein an upper surface of the upper surface passivation sub-layer defines an upper surface of the surface passivation.
However, Chen teaches forming the surface passivation ( Fig. 3A #146 ) includes forming a lower surface passivation sub-layer ( Fig. 3A #146 A ) on the upper surface of the semiconductor substrate ( Fig. 1 #140 is on the upper surface of the substrate ), an forming an intermediate surface passivation sub-layer ( Fig. 3A #146B ) on the lower surface passivation sub-layer ( Fig. 3A #146A ), and forming an upper surface passivation sub-layer ( Fig. 3A #146C ) on the intermediate surface passivation sub-layer ( Fig. 3A #146B ), wherein an upper surface of the upper surface passivation sub-layer defines an upper surface of the surface passivation ( as shown in Fig. 3A ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Chen with Fisher to implement forming the surface passivation includes forming a lower surface passivation sub-layer on the upper surface of the semiconductor substrate, forming an intermediate surface passivation sub-layer on the lower surface passivation sub-layer, and forming an upper surface passivation sub-layer on the intermediate surface passivation sub-layer, wherein an upper surface of the upper surface passivation sub-layer defines an upper surface of the surface passivation because this is a strategic approach to optimize the performance, reliability, and manufacturing efficiency of the device.
Claim 17 is rejected under U.S.C. 103 as being unpatentable over Fisher et al. US 2024/0162304 A1; ( CON of application filed 10/2020) in view of Chen et al.; US 2021/0407947 A1; 06/2020 as it related to claim 16 and further in view of Yin et al.; US 2012/0313149 A1; 08/2011
Claim 17: Fisher and Chen disclose the method of claim 16 ( as discussed above).
Neither Fisher nor Chen appear to disclose simultaneously forming a gate electrode opening and a field plate opening through the ILD0; forming field plate dielectric spacers in the field plate opening, wherein the field plate dielectric spacers contact sidewalls of the ILD0 and the upper surface of the surface passivation; and removing the upper surface passivation sub-layer between the field plate dielectric spacers to expose a portion of an upper surface of the intermediate surface passivation sub-layer, and wherein forming the conductive field plate includes forming the first field plate on the portion of the upper surface of the intermediate surface passivation sub-layer between the field plate dielectric spacers.
However, Yin teaches simultaneously forming a gate electrode opening and a field plate opening through the ILD0 ( [0033] etching the gate dielectric layer #111, the metal gate #112, the CMP stop layer #113 and the poly silicon layer #114 to form a gate stack ); forming field plate dielectric spacers in the field plate opening ( [0044] The sidewall spacers #116 are formed by means of deposition and etching process and its thickness may be in the range between nm and 100 nm for example 30 nm, 50 nm, or 80 nm ), wherein the field plate dielectric spacers ( Fig. 5 #116 ) contact sidewalls ( as shown in Fig. 5 ) of the ILD0 ( Fig. 5 #115 ) and the upper surface of the surface passivation ( Fig. 4 #114 ) ; and removing the upper surface passivation sub-layer ( Fig. 4 #114 ) between the field plate dielectric spacers ( Fig. 5 #116 ) to expose a portion of an upper surface of the intermediate surface passivation sub-layer ( Fig. 5 #113 ), and wherein forming the conductive field plate includes forming the first field plate ( Fig. 12 #121 ) on the portion of the upper surface of the intermediate surface passivation sub-layer ( Fig. 5 #113 ) between the field plate dielectric spacers ( Fig. 5 #116 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Yin with Fisher and Chen to implement simultaneously forming a gate electrode opening and a field plate opening through the ILD0; forming field plate dielectric spacers in the field plate opening, wherein the field plate dielectric spacers contact sidewalls of the ILD0 and the upper surface of the surface passivation; and removing the upper surface passivation sub-layer between the field plate dielectric spacers to expose a portion of an upper surface of the intermediate surface passivation sub-layer, and wherein forming the conductive field plate includes forming the first field plate on the portion of the upper surface of the intermediate surface passivation sub-layer between the field plate dielectric spacers because this approach creates self-aligned field-plated semiconductor devices with improved breakdown voltage and enhanced performance stability.
Claim 18 is rejected under U.S.C. 103 as being unpatentable over Fisher et al. US 2024/0162304 A1; ( CON of application filed 10/2020) in view of Chen et al.; US 2021/0407947 A1; 06/2020 as it related to claim 16 and further in view of Hu et al.; US 2024/0395872 A1; 05/2023
Claim 18: Fisher and Chen disclose the method of claim 16 ( as discussed above).
Neither Fisher nor Chen appear to disclose simultaneously forming a gate electrode opening and a field plate opening through the ILD0; forming field plate dielectric spacers in the field plate opening, wherein the field plate dielectric spacers contact sidewalls of the ILD0 and the upper surface of the surface passivation; and removing the upper surface passivation sub-layer and the intermediate surface passivation sub-layer between the field plate dielectric spacers to expose a portion of an upper surface of the lower surface passivation sub-layer, and wherein forming the conductive field plate includes forming the first field plate on the portion of the upper surface of the lower surface passivation sub-layer between the field plate dielectric spacers.
However, Hu teaches simultaneously forming a gate electrode opening and a field plate opening through the ILD0 ( Fig. 2 step #212 ); forming field plate dielectric spacers in the field plate opening ( [0203] In fabrication stage #906 (Fig. 9F), sidewall spacers 962, 963 are formed on the interior vertical sidewalls of the GFP alignment structures 162, 163 ), wherein the field plate dielectric spacers ( Fig. 9F #962 and #963 ) contact sidewalls of the ILD0 ( Fig. 9F #151 ) and the upper surface of the surface passivation ( ( [0029] In various embodiments, the surface passivation layer #130 is formed from multiple passivation sub-layers (e.g. layers #131, #132, #133 in FIGS. 3-9 )) ; and removing the upper surface passivation sub-layer ( Fig. 9F top layer of #130 removed ) and the intermediate surface passivation sub-layer ( Fig. 9 middle layer of #130 removed ) between the field plate dielectric spacers ( as shown in Fig. 9F ) to expose a portion of an upper surface of the lower surface passivation sub-layer ( as shown in Fig. 9F ), and wherein forming the conductive field plate includes forming the first field plate on the portion of the upper surface of the lower surface passivation sub-layer between the field plate dielectric spacers ( Fig. 9G #960 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Hu with Fisher and Chen to implement simultaneously forming a gate electrode opening and a field plate opening through the ILD0; forming field plate dielectric spacers in the field plate opening, wherein the field plate dielectric spacers contact sidewalls of the ILD0 and the upper surface of the surface passivation; and removing the upper surface passivation sub-layer and the intermediate surface passivation sub-layer between the field plate dielectric spacers to expose a portion of an upper surface of the lower surface passivation sub-layer, and wherein forming the conductive field plate includes forming the first field plate on the portion of the upper surface of the lower surface passivation sub-layer between the field plate dielectric spacers because this approach improves device performance specifically by increasing the breakdown voltage and managing the electric field distribution.
Claim 19 is rejected under U.S.C. 103 as being unpatentable over Fisher et al. US 2024/0162304 A1; in view of Cheng et al.; US 9269792 B2; 06/2014 as it relates to claim 15 above and further in view of Challa et al.; US 7,982,265 B2; 01/2008
Claim 19: Fisher discloses the method of claim 15 ( as discussed above).
Fisher does not appear to disclose simultaneously forming a gate electrode opening and a field plate opening through the ILD0; forming gate dielectric spacers in the gate electrode opening, wherein the gate dielectric spacers contact sidewalls of the ILD0 and the upper surface of the surface passivation; removing the surface passivation between the gate dielectric spacers to expose a portion of the upper surface of the semiconductor substrate; and removing the gate dielectric spacers so that the gate electrode opening has a first horizontal bottom extent that exposes the portion of the upper surface of the semiconductor substrate, a second horizontal bottom extent defined by the upper surface of the surface passivation, and a third horizontal bottom extent at or below an upper surface of the ILD0, and wherein forming the gate electrode includes depositing gate metal in the gate electrode opening to form the gate channel portion in contact with the upper surface of the semiconductor substrate at the first horizontal bottom extent of the gate electrode opening, the first gate field plate in contact with the upper surface of the surface passivation at the second horizontal bottom extent of the gate electrode opening, and the second gate field plate in contact with the third horizontal bottom extent of the gate electrode opening.
However, Cheng teaches simultaneously forming a gate electrode opening and a field plate opening through the ILD0 ( Fig. 4 ILD layer #30 recessed ); forming gate dielectric spacers ( Fig. 5 first spacer material layer #34 ) in the gate electrode opening ( Fig. 5 sacrificial gate structures #20 ), wherein the gate dielectric spacers ( Fig. 6 #36 ) contact sidewalls of the ILD0 ( Fig. 6 #32 ) and the upper surface of the surface passivation ( Fig. 6 #26 ) ; removing the surface passivation between the gate dielectric spacers to expose a portion of the upper surface of the semiconductor substrate ( Fig. 12 #45 ) and removing the gate dielectric spacers ( Fig. 7 #22’ ) so that the gate electrode opening has a first horizontal bottom extent that exposes the portion of the upper surface of the semiconductor substrate ( as shown in Fig. 14 ), a second horizontal bottom extent ( Fig. 8 #38 ) defined by the upper surface of the surface passivation (Fig. 6 # 26); the first gate field plate ( Fig. 14 gate cap #50 ) in contact with the upper surface of the surface passivation at the second horizontal bottom extent of the gate electrode opening ( Fig. 14 #48 ), and the second gate field plate in contact with the third horizontal bottom extent of the gate electrode opening ( Fig. 14 #38 ).
Cheng does not appear to disclose a third horizontal bottom extent at or below an upper surface of the ILD0, and wherein forming the gate electrode includes depositing gate metal in the gate electrode opening to form the gate channel portion in contact with the upper surface of the semiconductor substrate at the first horizontal bottom extent of the gate electrode opening.
However, Challa teaches a third horizontal bottom extent ( Fig. 20 #2010) at or below an upper surface of the ILD0 ( Fig. 20 #2008 ), and wherein forming the gate electrode includes depositing gate metal ( Col. 45 lines 9-10 In another embodiment, the poly gate is replaced by a metal gate ) in the gate electrode opening to form the gate channel portion ( Fig. 20 #2012 n- channel ) in contact with the upper surface of the semiconductor substrate ( Fig. 20 #2006 ) at the first horizontal bottom extent of the gate electrode opening ( Fig. 20 #2010 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Challa with Fisher and Cheng to implement a third horizontal bottom extent at or below an upper surface of the ILD0, and wherein forming the gate electrode includes depositing gate metal in the gate electrode opening to form the gate channel portion in contact with the upper surface of the semiconductor substrate at the first horizontal bottom extent of the gate electrode opening because this improves electrostatic control and prevents parasitic channels and leakage.
Claim 20 is rejected under U.S.C. 103 as being unpatentable over Fisher et al. US 2024/0162304 A1; in view of Ho et al.; US 11,335,784 B2; 11/2020
Claim 20: Fisher discloses the method of claim 15 ( as discussed above).
Fisher does not appear to disclose forming the conductive field plate includes: forming the conductive field plate to further include a third field plate with a fifth horizontal bottom extent that is higher than the fourth horizontal bottom extent of the second field plate.
However, Ho teaches forming the conductive field plate ( Fig. 3A #122 ) includes: forming the conductive field plate to further include a third field plate ( Fig. 3A #312c ) with a fifth horizontal bottom extent that is higher than the fourth horizontal bottom extent ( as shown in Fig. 3A) of the second field plate ( Fig. 3A #312b ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Ho with Fisher to implement forming the conductive field plate includes: forming the conductive field plate to further include a third field plate with a fifth horizontal bottom extent that is higher than the fourth horizontal bottom extent of the second field plate.
Claim 21 is rejected under U.S.C. 103 as being unpatentable over Fisher et al. US 2024/0162304 A1; in view of Ho et al.; US 11,335,784 B2; 11/2020 as it relates to claim 20 above and further in view of Djemour et al.; US 2022/0359314 A1; 05/2022
Claim 21: Fisher and Ho disclose the method of claim 20 ( as discussed above).
Neither Fisher nor Ho appear to disclose forming the ILD0 comprises: forming a lower ILD0 sub-layer on the upper surface of the surface passivation; forming an intermediate ILD0 sub-layer on an upper surface of the lower ILD0 sub-layer; and forming an upper ILD0 sub-layer on the upper surface of the intermediate ILD0 sub-layer, wherein the fourth horizontal bottom extent of the second field plate overlies and contacts the upper surface of the lower ILD0 sub-layer, the fifth horizontal bottom extent of the third field plate overlies and contacts an upper surface of the upper ILD0 sub-layer, and the second horizontal bottom extent of the second gate field plate overlies an upper surface of the intermediate ILD0 sub-layer.
However, Djemour teaches forming the ILD0 comprises: forming a lower ILD0 sub-layer ( [0102] The interlayer dielectric #210 may include one single homogeneous layer or may include two or more sub-layers of different composition and/or different density or stoichiometry ) on the upper surface of the surface passivation ( [0041] an interlayer dielectric may be formed between the first surface and the passivation layer ); forming an intermediate ILD0 sub-layer on an upper surface of the lower ILD0 sub-layer ( as discussed above ); and forming an upper ILD0 sub-layer on the upper surface of the intermediate ILD0 sub-layer ( as discussed above ), wherein the fourth horizontal bottom extent of the second field plate overlies and contacts the upper surface of the lower ILD0 sub-layer ( Fig. 1B #350 horizontal bottom contacts the upper surface of #210 ), the fifth horizontal bottom extent of the third field plate overlies and contacts an upper surface of the upper ILD0 sub-layer ( Fig. 1B horizontal portion of #350 on #210 ), and the second horizontal bottom extent of the second gate field plate overlies an upper surface of the intermediate ILD0 sub-layer ( Fig. 1B shows the bottom portion of #350 penetrates through #210 so it contacts the intermediate sub-layer ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Djemour with Fisher and Ho to implement forming the ILD0 comprises: forming a lower ILD0 sub-layer on the upper surface of the surface passivation; forming an intermediate ILD0 sub-layer on an upper surface of the lower ILD0 sub-layer; and forming an upper ILD0 sub-layer on the upper surface of the intermediate ILD0 sub-layer, wherein the fourth horizontal bottom extent of the second field plate overlies and contacts the upper surface of the lower ILD0 sub-layer, the fifth horizontal bottom extent of the third field plate overlies and contacts an upper surface of the upper ILD0 sub-layer, and the second horizontal bottom extent of the second gate field plate overlies an upper surface of the intermediate ILD0 sub-layer because this approach controls the electric field distribution, improves the break down voltage, and enhances the overall device reliability and performance.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIMBERLY N FREY whose telephone number is (571)272-5068. The examiner can normally be reached Monday - Friday 7:30 am - 5 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/K.N.F./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817