DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for priority under 35 U.S.C. 119(a)-(d) or (f), 365(a) or (b), or 386(a) based upon applications filed in the COUNTRY OF KOREA on 03/24/2023 and 04/26/2023.
Election/Restrictions
Applicant's election without traverse of “Species A (Claims 1-5,7 and 15-17)” in the reply filed on August 4, 2025, is acknowledged. Claims 6,8-14 and 18-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1,4,7 and 15 are rejected under 35 U.S.C. 103 as being obvious over US 12,166,034 B2; Wu et al.; 12/2024; (“034”).
Regarding Claim 1. 034 teaches in Figs. 1A and 1B about an integrated circuit device, comprising:
a pair of fin-type active regions (Fig. 1A, active regions of item 112 and 114) that extend in a first lateral direction (Fig. 1A, active regions extend in a direction along cross-sectional cut line XX’) on a substrate (Fig. 1B, item 102), wherein the pair of fin-type active regions are collinear with each other in the first lateral direction (Fig. 1A, active regions are collinear along cut line XX’);
a first gate line (Fig. 1A, bottom or top item 108) that extends in a second lateral direction (Fig. 1A, items 108 extend in a perpendicular direction to the cut line XX’ in the top-down layout of Fig. 1A) on one of the fin-type active regions (Fig. 1B, items 108 are on the fin-type active regions item 104), wherein the second lateral direction crosses the first lateral direction (Fig. 1A, the direction that gate lines extend crosses the direction that fin-type regions extend);
a capping insulating layer (Fig. 1B, item 166) that covers a top surface of the first gate line (Fig. 1B, item 166 covers the top surface of items 108); and
a fin isolation insulating portion (Fig. 1A, item 110) that extends in the second lateral direction between the pair of fin-type active regions (Fig. 1A, item 110 extends in the second direction between region items 112 and 114), wherein the fin isolation insulating portion passes through the capping insulating layer in a vertical direction (Fig. 1B, item 110 passes through item 166 in a vertical direction) that is perpendicular to a plane defined by the first lateral direction and the second lateral direction (vertical direction of Fig. 1B is perpendicular to the top-down layout plane of Fig. 1B),
wherein the fin isolation insulating portion comprises:
an isolation insulating plug (Fig. 1B, item 170) that includes a first portion (Fig. 1B, lower portion of item 170 below item 166) and a second portion (Fig. 1B, upper portion of item 170 at the same level as item 166), wherein the first portion is interposed between the pair of fin-type active regions (Fig. 1B, first portion of item 170 is interposed between fin-type active regions items 104 of transistor items 152 and 154), and the second portion is integrally connected to the first portion and passes through the capping insulating layer in the vertical direction (Fig. 1B, upper second portion of item 170 is integrally connected to lower first portion of item 170, and second portion passes through item 166 in the vertical direction); and
an isolation insulating liner (Fig. 1B, item 172) that surrounds a bottom surface and a sidewall of the isolation insulating plug (Fig. 1B, item 172 surrounds a bottom surface and a side wall of item 170), wherein the isolation insulating liner includes an uppermost portion that is equally distant to the substrate than a top surface of the isolation insulating plug.
636 does not teach about an integrated circuit device, comprising:
an isolation insulating liner wherein the isolation insulating liner includes an uppermost portion that is closer to the substrate than a top surf ace of the isolation insulating plug.
It would have been an obvious matter of design choice to reduce in a vertical direction the coverage of the isolation insulating liner around the isolation insulation plug (especially since the coverage vertical reduction of the isolation insulating liner around the isolation insulating plug only exposes the isolation insulation plug to another insulating layer item 166), since such a modification would have involved a mere change in the size of component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP 2144.04.
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Fig. 1A, annotated by Examiner from Wu et al., “034”
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Fig. 1B, annotated by Examiner from Wu et al., “034”
Regarding Claim 4. 034 teaches in Fig. 5B about an integrated circuit device, wherein each of the isolation insulating liner and the capping insulating layer comprises one of a silicon nitride film or a silicon carbonitride (SiCN) film (“SiN recap process 402 forms a layer of SiN 502 on the upper outer surfaces of the trench 310”, Col. 9, Ln. 1-3, and “insulating layer 166, such as silicon nitride”, Col. 4, Ln. 61-62), and
the isolation insulating plug comprises at least one of a silicon oxide film, a silicon oxynitride (Si ON) film, a silicon oxycarbonitride (SiOCN) film, a SiCN film, a silicon nitride film (“trench 310 is filled with SiN”, Col. 10, Ln. 13-14), or a combination thereof.
Regarding Claim 7. 034 teaches in Figs. 1B and 3 about an integrated circuit device, wherein at least one nanosheet disposed on the one selected fin-type active region, wherein the at least one nanosheet is surrounded by the first gate line (Fig. 3, “multi-channels provided by the nanosheet channels in the channel region 303a, 303b of the first GAA transistor device 352 and the second GAA transistor device 354”, Col. 6, Ln. 49-52);
a source/drain region disposed on the one selected fin-type active region between the first gate line and the fin isolation insulating portion (Fig. 3, source/drain region items 305b and 305c are disposed between gate line items 308a and 308 respectively, and the isolation insulating portion item 310); and
an inter-gate dielectric film that covers the source/drain region (Fig. 1B, items 164 covers items 105), wherein the inter-gate dielectric film is interposed between the first gate line and the fin isolation insulating portion in the first lateral direction (Fig. 1B, items 164 are interposed between gate line items 108 and the isolation insulating portion item 110),
wherein the capping insulating layer covers a top surface of the inter-gate dielectric film (Fig. 1B, item 166 covers a top surface of item 164).
Regarding Claim 15. 034 teaches in Figs. 1A,1B and 3 about an integrated circuit device, comprising:
a pair of fin-type active regions (Fig. 1A, active regions of item 112 and 114) that extend in a first lateral direction (Fig. 1A, active regions extend in a direction along cross-sectional cut line XX’) on a substrate (Fig. 1B, item 102), wherein the pair of fin-type active regions are collinear with each other in the first lateral direction (Fig. 1A, active regions are collinear along cut line XX’);
a fin isolation insulating portion (Fig. 1A, item 110) that extends in a second lateral direction between the pair of fin-type active regions (Fig. 1A, item 110 extends in the second direction between region items 112 and 114), wherein the second lateral direction crosses the first lateral direction (see Fig. 1A annotated by Examiner);
a pair of nanosheet stacks respectively disposed on the pair of fin-type active regions, wherein each nanosheet stack includes at least one nanosheet line (Fig. 3, “multi-channels provided by the nanosheet channels in the channel region 303a, 303b of the first GAA transistor device 352 and the second GAA transistor device 354”, Col. 6, Ln. 49-52);
a first pair of gate lines (Fig. 3, item 308a and 308b) that surround the at least one nanosheet on the pair of fin-type active regions (Fig. 3, “multi-channels provided by the nanosheet channels in the channel region 303a, 303b of the first GAA transistor device 352 and the second GAA transistor device 354”, Col. 6, Ln. 49-52), wherein the first pair of gate lines extend in the second lateral direction (see Fig. 1A annotated by Examiner, wherein gate line items 108 extend in the second lateral direction);
a capping insulating layer (Fig. 1B, item 166) that covers top surfaces of the first pair of gate lines (Fig. 1B, item 166 covers the top surfaces of the pair of items 108); and
a pair of source/drain regions respectively disposed on both sides of the fin isolation insulating portion between the first pair of gate lines (Fig. 1B, items 105 respectively disposed on both sides of item 110 between gate line items 108),
wherein the fin isolation insulating portion comprises:
an isolation insulating plug (Fig. 1B, item 170) that includes a first portion (Fig. 1B, lower portion of item 170 below item 166) and a second portion (Fig. 1B, upper portion of item 170 at the same level as item 166), wherein the first portion is disposed between the pair of fin-type active regions (Fig. 1B, first portion of item 170 is disposed between fin-type active regions items 104 of transistor items 152 and 154), and the second portion is integrally connected to the first portion and passes through the capping insulating layer in a vertical direction (Fig. 1B, upper second portion of item 170 is integrally connected to lower first portion of item 170, and second portion passes through item 166 in the vertical direction) that is perpendicular to a plane defined by the first lateral direction and the second lateral direction; and
an isolation insulating liner (Fig. 1B, item 172) that surrounds a bottom surface and a sidewall of the isolation insulating plug (Fig. 1B, item 172 surrounds a bottom surface and a side wall of item 170), wherein the isolation insulating liner includes an uppermost portion that is equally distant to the substrate than a top surface of the isolation insulating plug.
636 does not teach about an integrated circuit device, comprising:
an isolation insulating liner wherein the isolation insulating liner includes an uppermost portion that is closer to the substrate than a top surf ace of the isolation insulating plug.
It would have been an obvious matter of design choice to reduce in a vertical direction the coverage of the isolation insulating liner around the isolation insulation plug (especially since the coverage vertical reduction of the isolation insulating liner around the isolation insulating plug only exposes the isolation insulation plug to another insulating layer item 166), since such a modification would have involved a mere change in the size of component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP 2144.04.
Allowable Subject Matter
Claims 2-3,5 and 16-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art does not teach or suggest the claimed limitations.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JORGE ANDRES LOPEZ whose telephone number is (571)272-5763. The examiner can normally be reached M-F (8:30am to 5:00pm).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/JORGE ANDRES LOPEZ/Examiner, Art Unit 2897
Prosecution Insights