DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 4 – 5 & 15 – 16 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 5 March 2026.
Applicant’s election without traverse of Species IV, as presented in at least Fig. 10B, in the aforementioned reply is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: MEMORY DEVICE WITH PATTERNED METALLIC SOURCE LAYER
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 – 3, 6 – 14, & 17 – 18 is/are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by CHOI (US 20230021449 A1).
Examiner’s Note
For the following rejection, consider both the original figures of CHOI and the cropped annotated figure of CHOI provided below.
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Regarding Claim 1,
CHOI discloses:
A semiconductor device (Fig. 2 – 4B; Par. 36) comprising:
a gate structure (220/230) including gate lines (230) extending in a first direction (Y);
a first source pattern (201) located on the gate structure (220/230);
second source patterns (260) spaced apart from each other along the first direction (Y),
(As seen in Fig. 2)
the second source patterns (260) located on the first source pattern (201) and extending in a second direction (X) intersecting the first direction (Y); and
(As seen in Fig. 3)
channel structures (CH) spaced apart from each other along the first direction (Y),
(As seen in Fig. 2)
each channel structure (CH) extending through the gate structure (220/230) and protruding into the first source pattern (201).
(As seen in Fig. 2)
Regarding Claim 2,
CHOI discloses:
The semiconductor device of claim 1, wherein
the second source patterns (260) include a material having a lower specific resistance than the first source pattern (201).
(Par. 76: 260 may include copper; Par. 51: 201 may be polysilicon. Inherently, copper has a lower specific resistance than polysilicon.)
Regarding Claim 3,
CHOI discloses:
The semiconductor device of claim 1, wherein
the first source pattern (201) includes polysilicon (Par. 51), and
the second source patterns (260) include metal (Par. 76).
Regarding Claim 6,
CHOI discloses:
The semiconductor device of claim 1, wherein
the gate structure (220/230) includes a cell region (MCA) and a contact region (PA/CA), and
the channel structures (CH) are located in the cell region (MCA).
(As seen in Fig. 2)
Regarding Claim 7,
CHOI discloses:
The semiconductor device of claim 6, further comprising
contact plugs (252) respectively connected to the gate lines (230) in the contact region (PA/CA). (As seen in Fig. 2)
Regarding Claim 8,
CHOI discloses:
The semiconductor device of claim 6, wherein
the first source pattern (201) and the second source patterns (260) are located on the cell region (MCA).
(As seen in Fig. 2)
Regarding Claim 9,
CHOI discloses:
The semiconductor device of claim 1, further comprising:
a first interconnection structure (270) located below the gate structure (220/230) and connected to the channel structures (CH);
(As seen in Fig. 2)
a peripheral circuit (PERI);
a second interconnection structure (130) connected to the peripheral circuit (PERI); and
(As seen in Fig. 2)
a bonding structure (180/280) electrically connecting the first interconnection structure (270) and the second interconnection structure (130) to each other. (As seen in Fig. 2)
Regarding Claim 10,
CHOI discloses:
The semiconductor device of claim 1, further comprising
first insulating layers (210) respectively located between the second source patterns (260) and
(“Between” may be defined as “in [a] time, space, or interval that separates”, as per www.merriam-webster.com. Further, one such interval that separates the second source patterns 260 is the interval defined by the arc ARC, as provided in Fig. 2. In such intervals, it can be seen that the first insulating layers 210 are respectively located between the second source patterns 260.)
extending in the second direction (X).
(Second source patterns 260 are clearly three-dimensional. As such, second source patterns 260 extend in every direction, including the second direction X.)
Regarding Claim 11,
CHOI discloses:
The semiconductor device of claim 10, wherein
the gate structure (220/230) includes a cell region (MCA) and a contact region (PA/CA), and
the semiconductor device (Fig. 2 – 4B) further comprising
a second insulating layer (205) located on the contact region (PA of PA/CA).
(As seen in Fig. 2)
Regarding Claim 12,
CHOI discloses:
The semiconductor device of claim 11, wherein
a level of a lower surface of the second insulating layer (205) is located below a level of a lower surface of each of the first insulating layers (210).
(As seen in Fig. 2)
Regarding Claim 13,
CHOI discloses:
A semiconductor device (Fig. 2 – 4B; Par. 36) comprising:
a gate structure (220/230) including a cell region (MCA) and a contact region (PA/CA) and including gate lines (230) extending in a first direction (Y);
a first source pattern (201) located on the cell region (MCA) of the gate structure (220/230);
second source patterns (260) located on the first source pattern (201) and extending in a second direction (X) intersecting the first direction (Y);
first insulating layers (210) respectively located between the second source patterns (260); and
(As explained in the rejection of Claim 10)
a second insulating layer (205) located on the contact region (PA of PA/CA).
(All limitations visible in Fig. 2 & 3)
Regarding Claim 14,
CHOI discloses:
The semiconductor device of claim 13, wherein
the second source patterns (260) include a material having a lower specific resistance than the first source pattern (210).
(Par. 76: 260 may include copper; Par. 51: 201 may be polysilicon. Inherently, copper has a lower specific resistance than polysilicon.)
Regarding Claim 17,
CHOI discloses:
The semiconductor device of claim 13, further comprising:
channel structures (CH) located in the cell region (MCA); and
contact plugs (252) respectively connected to the gate lines (230) in the contact region (PA/CA).
(As seen in Fig. 2)
Regarding Claim 18,
CHOI discloses:
The semiconductor device of claim 17, further comprising:
a first interconnection structure (270) located below the gate structure (220/230) and connected to the channel structures (CH);
(As seen in Fig. 2)
a peripheral circuit (PERI);
a second interconnection structure (130) connected to the peripheral circuit (PERI); and
a bonding structure (180/280) electrically connecting the first interconnection structure (270) and the second interconnection structure (130) to each other.
(As seen in Fig. 2)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kenneth S. Stephenson whose telephone number is (571)272-6686. The examiner can normally be reached Monday through Friday, 9 A.M. to 5 P.M. (EST)..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/K.S.S./Examiner, Art Unit 2898
/JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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