CTNF 18/499,266 CTNF 98676 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. DETAILED ACTION This Office Action is in response to Applicant’s Response to Election/Restriction Requirement received on May 6, 2026, regarding the application filed November 1, 2023. Election/Restrictions Applicant’s election without traverse of Invention I, corresponding to claims 1-10 and 18-20, in the reply filed on May 6, 2026 is acknowledged. Claims 11-17 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. This restriction requirement has been finalized. Claims 1-20 are pending, with claims 11-17 currently withdrawn from consideration. Information Disclosure Statement The information disclosure statement (IDS) submitted on November 1, 2023 has been placed in the application file and is being considered by the examiner. Drawings The drawings filed with the application on November 1, 2023 are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters "102" and "112" have both been used to designate backside BEOL structure ; reference characters "600" and "610" have both been used to designate dielectric layer ; reference characters "100" and "110" have both been used to designate first device layer ; reference characters "5211" and "5311" have both been used to designate first section ; reference characters "501" “511” “521” “531” and “541” have been used to designate first type via connection ; reference characters "202" and "212" have both been used to designate frontside BEOL structure ; reference characters "400” “401” “402” “4021” “410” “411” and “412” have been used to designate large pitch wires ; reference characters "500” “510” “520” and “540” have been used to designate middle BEOL structure ; reference characters "200" and "210" have both been used to designate second device layer ; reference characters "5212" and "5312" have both been used to designate second section ; reference characters "502" "512" “522” and “542” have been used to designate second type via connection ; reference characters "10" "20" “30” “40” and “50” have been used to designate semiconductor structure ; reference characters "300" "301" “302” “3021” “310” and “311” have been used to designate small pitch wires . See MPEP 608.02(e). The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the first type via connection from the second device layer to the multiple layers of small pitch wires , as recited in claims 1 and 18; the second type via connection from the second device layer to the multiple layers of large pitch wires , as recited in claim 6; the third type via connection from the second device layer to the multiple layers of large pitch wires , as recited in claim 8; and the second type and a third type via connection form the second device layer to the multiple layers of large pitch wires , as recited in claim 18 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Applicant’s drawings show via connection from the second device layer to a single layer of small pitch wires, and from the second device layer to a single layer of large pitch wires. Each via connection shown is only connected to a single layer of wires, and not to multiple layers of wires, as recited in the claims. 06-22 Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. 06-27 AIA In addition to Replacement Sheets containing the corrected drawing figure(s), applicant is required to submit a marked-up copy of each Replacement Sheet including annotations indicating the changes made to the previous version. The marked-up copy must be clearly labeled as “Annotated Sheets” and must be presented in the amendment or remarks section that explains the change(s) to the drawings. See 37 CFR 1.121(d)(1). Failure to timely submit the proposed drawing and marked-up copy will result in the abandonment of the application. Claim Objections 07-29-01 AIA Claim 18, and claims 19-20 dependent therefrom, are objected to because of the following informalities: claim 18 recites, inter alia , “a third type via connection form the second device layer”. This appears to be a typo and has been interpreted as “a third type via connection from the second device layer” . Appropriate correction is required. 07-05-05 Applicant is advised that should claim 18 be found allowable, claim 8 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m). Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 1-10 and 18-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The terms “small” and “large” in independent claims 1 and 18 are relative terms which renders the claims indefinite; claims 2-10 and 19-20 depend directly or indirectly from independent claims 1 and 18. The terms “small” and “large” are not defined by the claims, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. This rejection may be overcome by amending the claims to clearly recited the metes and bounds of the claims such that a person having ordinary skill in the art would be able to recognize the intended scope. See MPEP 2173.02. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-10 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hong et al., US 2023/0253324 A1 (hereinafter Hong ) in view of Elsherbini et al., US 2021/0407903 A1 (hereinafter Elsherbini ) . Regarding claim 1 , insofar as the claim can be understood in view of the 35 USC 112 rejections or claim objections above, Hong discloses: A semiconductor structure comprising: a first device layer ( Hong , FIG. 3 shows the first device layer as the lowermost FEOL layer that includes semiconductor devices 130, interlayer dielectric 140, and MOL contact structures 150, [0052]) on top of a backside back-end-of-line (BEOL) structure ( Hong , FIG. 3, lowermost BEOL layer 190, [0051]) ; a middle BEOL structure on top of the first device layer (the term “middle BEOL structure” does not appear to be a term commonly used in the art, and has therefore been interpreted as a dielectric layer with embedded wires and/or vias, support for this interpretation may be found in Applicant’s specification at [0026-0028]; Hong , FIG. 3 shows the middle BEOL structure as the middle layer including STI structures 120, inter-dielectric layer 140′, and backside power rails 160, [0052-0053]; “the BEOL layer may be divided into two BEOL layers with the FEOL layer and the MOL layer therebetween,” [0045]) ; a second device layer ( Hong , FIG. 3 shows the second device layer as the uppermost FEOL layer that includes semiconductor devices 130, interlayer dielectric 140, and MOL contact structures 150, [0054-0055]) on top of the middle BEOL structure ( Hong , see FIG. 3, [0055]) ; and a frontside BEOL structure on top of the second device layer ( Hong , FIG. 3, uppermost BEOL layer 190, [0051]) , wherein the middle BEOL structure includes multiple layers of small pitch wires; multiple layers of large pitch wires on top of the multiple layers of small pitch wires; and a first type via connection from the second device layer to the multiple layers of small pitch wires. Although Hong teaches BEOL vias extending from the BEOL layer to an MOL layer ( Hong, [0051]), Hong is silent regarding: wherein the middle BEOL structure includes multiple layers of small pitch wires; multiple layers of large pitch wires on top of the multiple layers of small pitch wires; and a first type via connection from the second device layer to the multiple layers of small pitch wires. However, Elsherbini , in the same field of endeavor, teaches a dielectric material with embedded signal traces and power traces, i.e., wires, and vias, for interconnecting multilevel semiconductor devices; this is analogous to Applicant’s claimed middle BEOL structure . Elsherbini teaches that traces, i.e., wires, provided in adjacent planes, i.e., in multiple layers, can include multiple layers of small pitch wires ( Elsherbini , FIGs. 4A and 4B, traces 401-403, “Additional conductor planes may be present below level N-3 (e.g., N-4, N-5, etc.). Traces 401-403 have thicknesses ranging between 10 and 50 microns,” [0073]); multiple layers of large pitch wires ( Elsherbini , FIGs. 4A and 4B, traces 402-403, “traces 402 and 403 are power traces, which may have larger critical dimensions (e.g., thickness or width) larger than traces (e.g., trace 401),” [0073]); and a first type via connection from the second device layer to the multiple layers of small pitch wires ( Elsherbini , FIG. 4E, power via 408, shown extending from lower surface of pads 410, analogous to the connection to the second device layer, to the embedded traces). Although Elsherbini is silent regarding a via connection to the multiple layers of small pitch wires, a person having ordinary skill in the art before the effective filing date of the claimed invention would have understood that the multiple layers of embedded signal traces, i.e., the small pitch wires, would require a via connection to electrically couple the multiple layers of signal traces to the device layer for device functionality. For example, Elsherbini teaches that “the metallization pattern [the layers of wires] may comprise integrated signal and/or power routing, the latter comprising conductors such as traces and pads that may generally be larger [the multiple layers of large pitch wires] than signal routing conductors that carry small signals [the multiple layers of small pitch wires], [0032-0034]). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Hong with the teachings of Elsherbini , arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as recognized by Elsherbini , to provide for device functionality by connecting appropriate vias to the embedded traces while minimizing interference with signal routing, thereby improving device performance and reliability. Regarding claim 2 , Hong in view of Elsherbini teaches nearly every element of claim 2 but is silent regarding: wherein a pitch of the large pitch wires is greater than three times a pitch of the small pitch wires. However, Elsherbini teaches that the distance between the embedded traces, i.e., the pitch of the wires, is optimized to minimize interference with signal routing and power traces, and that the distance, i.e., the pitch, may be determined based on the locations and orientations of the signal traces and power traces ( Elsherbini , [0050]). Furthermore, Elsherbini teaches that “traces 203 may be representative of multiple signal traces that are part of signal routing in conductor plane N-3. … trace 202 (and other power carrying conductors) within may have a greater thickness and/or width than traces 203 (having width w1) to increase cross sectional area, reducing resistance,” ( Elsherbini , [0046]). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to arrive at Applicant’s claimed structural arrangement, wherein a pitch of the large pitch wires is greater than three times a pitch of the small pitch wires , with a high likelihood of success and without undue experimentation. The motivation for doing so would be, as recognized by Elsherbini , to allow space for power traces having increased cross sectional area, while also minimizing interference with signal and power traces, thereby improving device performance and reliability. Regarding claim 3 , Hong in view of Elsherbini teaches nearly every element of claim 3 but is silent regarding: wherein a height of one of the large pitch wires is greater than three times a height of one of the small pitch wires. However, Elsherbini teaches that the height of the embedded traces, i.e., the wires, is optimized to improve electrical characteristics such as current carrying capacity, while reducing electroplating costs ( Elsherbini , [0049]). Elsherbini teaches that it is advantageous to provide the power trace with a larger height ( Elsheribini , [0049]). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to arrive at Applicant’s claimed structural arrangement, wherein a height of one of the large pitch wires is greater than three times a height of one of the small pitch wires , with a high likelihood of success and without undue experimentation. Regarding claim 4 , Hong in view of Elsherbini teaches: The semiconductor structure of claim 1, wherein the first type via connection is a continuous via ( Elsherbini , FIG. 4E, power via 408 shown as a continuous via) . Regarding claim 5 , Hong in view of Elsherbini teaches: The semiconductor structure of claim 1, wherein the first type via connection is a stacked via made of at least two connected vias ( Elsherbini , “ Multiple via stacks may be employed to interconnect power planes separated by several dielectric layers,” [0065; see also [0040] describing stacks of microvias employed for vertical interconnects]) . Regarding claim 6 , Hong in view of Elsherbini teaches: The semiconductor structure of claim 1, further comprising a second type via connection from the second device layer to the multiple layers of large pitch wires ( Elsherbini , FIG. 4E, power via 409 [the second type via connection] shown extending from lower surface of pads 411, analogous to the connection to the second device layer, to the embedded traces 403, configured as power traces, [the multiple layers of large pitch wires], [0078]) . Regarding claim 7 , Hong in view of Elsherbini teaches every element of claim 6 but is silent regarding: wherein the first type via connection has an aspect ratio that is greater than four times an aspect ratio of the second type via connection. However, Elsheribini teaches that the aspect ratio of via holes 406 and 407, analogous to the first type via connection and the second type via connection, is selected based on the thickness of material through which the via extends ( Elsheribini , FIGs. 4B-4D, [0076]). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Elsheribini , insofar as selecting the aspect ratio of each of the first type via connection and the second type via connection from the finite number of predictable solutions, with a reasonable expectation of success and without undue experimentation. Regarding claim 8 , Hong in view of Elsherbini teaches: The semiconductor structure of claim 6, further comprising a third type via connection from the second device layer to the multiple layers of large pitch wires ( Elsheribini , “ third via comprising the second metal, wherein the third via extends from the upper-level conductor plane, to a third lower-level conductor plane, below the second lower-level conductor plane,” [0134]) , wherein the third type via connection has an aspect ratio that is greater than two times the aspect ratio of the second type via connection . Hong in view of Elsherbini is silent regarding: the third type via connection has an aspect ratio that is greater than two times the aspect ratio of the second type via connection. However, as discussed above, regarding claim 7, Elsheribini teaches that the aspect ratio of via holes is selected based on the thickness of material through which the via extends ( Elsheribini , [0076]). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Elsheribini , insofar as selecting the aspect ratio of each of the third type via connection and the second type via connection from the finite number of predictable solutions, with a reasonable expectation of success and without undue experimentation. Regarding claim 9 , Hong in view of Elsherbini teaches nearly every element of claim 8 but is silent regarding: wherein the second type via connection and the third type via connection have a substantially same height. However, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to arrive at Applicant’s claimed structural arrangement, wherein the second type via connection and the third type via connection have a substantially same height, because, a person having ordinary skill in the art would have recognized that in order to provide for device functionality, the upper surface, i.e., the height, of each via contacting the lower surface of the device layer would need to be co-planar; see, for example, FIG. 4D of Elsherbini , showing two vias with co-planar upper surfaces at the same height. Note that Applicant has defined the term substantially , “’substantially’ as used herein implies that a small margin of error may be present such as, by way of example only, 1% or less than the stated amount,” (Applicant’s specification, [0023]). Regarding claim 10 , Hong in view of Elsherbini teaches: The semiconductor structure of claim 8, wherein the first type, the second type, and the third type via connection are made of a metal ( Elsherbini , via connections are made of copper applied by electroplating process, [0045]) different from a material of the middle BEOL structure ( Hong , FIG. 3 shows the middle BEOL structure as the middle layer including STI structures 120, inter-dielectric layer 140′, and backside power rails 160, [0052-0053]; the material of inter-dielectric layer 140′, i.e., a material of the middle BEOL structure, is formed of SiO or SiN, [0052]) . Regarding claim 18 , insofar as the claim can be understood in view of the 35 USC 112 rejections or claim objections above, Hong discloses: A semiconductor structure comprising: a first device layer ( Hong , FIG. 3 shows the first device layer as the lowermost FEOL layer that includes semiconductor devices 130, interlayer dielectric 140, and MOL contact structures 150, [0052]) on top of a backside back-end-of-line (BEOL) structure ( Hong , FIG. 3, lowermost BEOL layer 190, [0051]) ; a middle BEOL structure on top of the first device layer (the term “middle BEOL structure” does not appear to be a term commonly used in the art, and has therefore been interpreted as a dielectric layer with embedded wires and/or vias, support for this interpretation may be found in Applicant’s specification at [0026-0028]; Hong , FIG. 3 shows the middle BEOL structure as the middle layer including STI structures 120, inter-dielectric layer 140′, and backside power rails 160, [0052-0053]; “the BEOL layer may be divided into two BEOL layers with the FEOL layer and the MOL layer therebetween,” [0045]) , the middle BEOL structure including multiple layers of small pitch wires and multiple layers of large pitch wires on top of the multiple layers of small pitch wires ; a second device layer ( Hong , FIG. 3 shows the second device layer as the uppermost FEOL layer that includes semiconductor devices 130, interlayer dielectric 140, and MOL contact structures 150, [0054-0055]) on top of the middle BEOL structure ( Hong , see FIG. 3, [0055]) ; a frontside BEOL structure on top of the second device layer ( Hong , FIG. 3, uppermost BEOL layer 190, [0051]) ; a first type via connection from the second device layer to the multiple layers of small pitch wires; and a second type and a third type via connection from [[form]] the second device layer to the multiple layers of large pitch wires . Hong is silent regarding: the middle BEOL structure including multiple layers of small pitch wires and multiple layers of large pitch wires on top of the multiple layers of small pitch wires … a first type via connection from the second device layer to the multiple layers of small pitch wires; and a second type and a third type via connection from the second device layer to the multiple layers of large pitch wires. However, Elsherbini , in the same field of endeavor, teaches a dielectric material with embedded signal traces and power traces, i.e., wires, and vias, for interconnecting multilevel semiconductor devices; this is analogous to Applicant’s claimed middle BEOL structure . Elsherbini teaches that traces, i.e., wires, provided in adjacent planes, i.e., in multiple layers, can include multiple layers of small pitch wires ( Elsherbini , FIGs. 4A and 4B, traces 401-403, “Additional conductor planes may be present below level N-3 (e.g., N-4, N-5, etc.). Traces 401-403 have thicknesses ranging between 10 and 50 microns,” [0073]); multiple layers of large pitch wires ( Elsherbini , FIGs. 4A and 4B, traces 402-403, “traces 402 and 403 are power traces, which may have larger critical dimensions (e.g., thickness or width) larger than traces (e.g., trace 401),” [0073]); and a first type via connection from the second device layer to the multiple layers of small pitch wires ( Elsherbini , FIG. 4E, power via 408, shown extending from lower surface of pads 410, analogous to the connection to the second device layer, to the embedded traces); and a second type via connection from the second device layer to the multiple layers of large pitch wires ( Elsherbini , FIG. 4E, power via 409 [the second type via connection] shown extending from lower surface of pads 411, analogous to the connection to the second device layer, to the embedded traces 403, configured as power traces, [the multiple layers of large pitch wires], [0078]); and a third type via connection from the second device layer to the multiple layers of large pitch wires ( Elsheribini , “third via comprising the second metal, wherein the third via extends from the upper-level conductor plane, to a third lower-level conductor plane, below the second lower-level conductor plane,” [0134]). Although Elsherbini is silent regarding a via connection to the multiple layers of small pitch wires, a person having ordinary skill in the art before the effective filing date of the claimed invention would have understood that the multiple layers of embedded signal traces, i.e., the small pitch wires, would require a via connection to electrically couple the multiple layers of signal traces to the device layer for device functionality. For example, Elsherbini teaches that “the metallization pattern [the layers of wires] may comprise integrated signal and/or power routing, the latter comprising conductors such as traces and pads that may generally be larger [the multiple layers of large pitch wires] than signal routing conductors that carry small signals [the multiple layers of small pitch wires], [0032-0034]). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Hong with the teachings of Elsherbini , arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as recognized by Elsherbini , to provide for device functionality by connecting appropriate vias to the embedded traces while minimizing interference with signal routing, thereby improving device performance and reliability. Regarding claim 19 , Hong in view of Elsherbini teaches nearly every element of claim 19 but is silent regarding: wherein the first type via connection has an aspect ratio that is greater than four times an aspect ratio of the second type via connection. However, Elsheribini teaches that the aspect ratio of via holes 406 and 407, analogous to the first type via connection and the second type via connection, is selected based on the thickness of material through which the via extends ( Elsheribini , FIGs. 4B-4D, [0076]). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Elsheribini , insofar as selecting the aspect ratio of each of the first type via connection and the second type via connection from the finite number of predictable solutions, with a reasonable expectation of success and without undue experimentation. Regarding claim 20 , Hong in view of Elsherbini teaches: The semiconductor structure of claim 18, wherein the backside BEOL structure ( Hong , FIG. 3, lowermost BEOL layer 190, [0051]) is a backside power distribution network (BSPDN) ( Hong , FIG. 3, see [0050-0053] describing BSPDN semiconductor chip stack structure) . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to Applicant’s disclosure. The cited prior art discloses similar materials, devices, and methods . Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEREK NIELSEN whose telephone number is (703)756-1266. The examiner can normally be reached Monday - Friday, 8:30 A.M. - 5:30 P.M.. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BRENT A FAIRBANKS can be reached at (408)918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /D.L.N./Examiner, Art Unit 2899 /Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899 Application/Control Number: 18/499,266 Page 2 Art Unit: 2899 Application/Control Number: 18/499,266 Page 3 Art Unit: 2899 Application/Control Number: 18/499,266 Page 4 Art Unit: 2899 Application/Control Number: 18/499,266 Page 5 Art Unit: 2899 Application/Control Number: 18/499,266 Page 6 Art Unit: 2899 Application/Control Number: 18/499,266 Page 7 Art Unit: 2899 Application/Control Number: 18/499,266 Page 8 Art Unit: 2899 Application/Control Number: 18/499,266 Page 9 Art Unit: 2899 Application/Control Number: 18/499,266 Page 10 Art Unit: 2899 Application/Control Number: 18/499,266 Page 11 Art Unit: 2899 Application/Control Number: 18/499,266 Page 12 Art Unit: 2899 Application/Control Number: 18/499,266 Page 13 Art Unit: 2899 Application/Control Number: 18/499,266 Page 14 Art Unit: 2899 Application/Control Number: 18/499,266 Page 15 Art Unit: 2899
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