DETAILED ACTION
Response to Arguments
Applicant’s arguments with respect to claims 1-16 have been considered but are moot based on the new grounds of rejection.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7, 9, 11, 12, 21 and 22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by PIROVANO et al. (US 20190252606 A1), hereinafter “Pirovano.”
Re: Independent Claim 1, Pirovano discloses a memory device comprising an ovonic memory element (See Figs. 3, 5, 7 and 8; Fig. 3: memory device 302 and memory component 220-a, i.e., ovonic memory element; ¶0068: self-selecting memory component 220-a may be a chalcogenide material, i.e., ovonic), wherein the ovonic memory element comprises:
a first electrode (Fig. 3: bottom electrode 210-a);
a second electrode (Fig. 3: top electrode 205-a); and
an ovonic threshold switching material portion located between the first electrode and the second electrode (Fig. 3: self-selecting memory component 220-a between first 210-a and second 205-a electrodes),
wherein a first interface area at which the ovonic threshold switching material portion contacts the first electrode is greater than a second interface area at which the ovonic threshold switching material portion contacts the second electrode (Fig. 3: first interface area 315 on the top surface of electrode 210-a, i.e., first electrode, is greater in area than the second interface area 310 located between the top surface of self-selecting memory component 220-a and the bottom surface of electrode 205-a, i.e., second electrode).
Re: Claim 2, Pirovano discloses the memory device of Claim 1, and wherein:
the first interface area is located at a first surface of the first electrode (Fig. 3: first interface area 315 is located between first/top surface of first electrode 210-a and bottom surface of self-selecting memory component 220-a);
the second interface area is located at a first surface of the second electrode (Fig. 3: second interface area 310 is located between first/bottom surface of second electrode 205-a and top surface of self-selecting memory component 220-a); and
the first surface of the first electrode has a greater lateral dimension along a first horizontal direction than the first surface of the second electrode (Fig. 3: first/top surface of first electrode 210-a has a greater lateral/horizontal dimension than the first surface of the second electrode 205-a).
Re: Claim 3, Pirovano discloses the memory device of Claim 2, and
wherein the first electrode is located below the second electrode (Fig. 3: first electrode 210-a is located below second electrode 205-a).
Re: Claim 4, Pirovano discloses the memory device of Claim 3, and wherein:
the first interface area is located at a first surface of the ovonic threshold switching material portion (Fig. 3: first interface area 315 is located between top surface of electrode 210-a and first/bottom surface of self-selecting memory component 220-a);
the second interface area is located at a second surface of the ovonic threshold switching material portion (Fig. 3: second interface area 310 is located between bottom surface of electrode 205-a and second/top surface of self-selecting memory component 220-a);
the first surface of the ovonic threshold switching material portion comprises a bottom surface (Fig. 3: self-selecting memory component 220-a has a bottom surface 315, i.e., first surface);
the second surface of the ovonic threshold switching material portion comprises a top surface (Fig. 3: self-selecting memory component 220-a has a top surface 310, i.e., second surface);
the first surface of the first electrode comprises a top surface (Fig. 3: first electrode 210-a has a top surface, i.e., first surface); and
the first surface of the second electrode comprises a bottom surface (Fig. 3: second electrode 205-a has a bottom surface, i.e., first surface).
Re: Claim 5, Pirovano discloses the memory device of Claim 2, and wherein:
the first electrode is located above the second electrode (Fig. 4 shows an embodiment 400-a with a first electrode 205-b is above a second electrode 210b);
the first interface area is located at a first surface of the ovonic threshold switching material portion (Fig. 4: first interface area 310-a is located at a first/top surface of self-selecting memory component 220-b);
the second interface area is located at a second surface of the ovonic threshold switching material portion (Fig. 4: second interface area 315-a is located a second/bottom surface of surface of self-selecting memory component 220-b);
the first surface of the ovonic threshold switching material portion comprises a top surface (Fig. 4: first/top surface 310-a of self-selecting memory component 220-b);
the second surface of the ovonic threshold switching material portion comprises a bottom surface (Fig. 4: second/bottom surface 315-a of self-selecting memory component 220-b);
the first surface of the first electrode comprises a bottom surface (Fig. 4: first surface of first electrode 205-b is a bottom surface located at 310-a); and
the first surface of the second electrode comprises a top surface (Fig. 4: first surface of second electrode 210-b is a top surface located at 315-a).
Re: Claim 6, Pirovano discloses the memory device of Claim 1, and
wherein the second interface area is located at a first segment of a second surface of the ovonic threshold switching material portion (See Figs. 3 and 7; Fig. 3: second interface area 310 of self-selecting memory component 220-a has edge portions, i.e., segments, on the second/top surface of 220-a; In other words, second interface area 310 is divided into segments, i.e., first central segment of the second/top surface of OTS element, and a segment outside of the central portion of the OTS element), and
the memory device further comprises a dielectric spacer contacting a sidewall of the second electrode and a second segment of the second surface of the ovonic threshold switching material portion (See Figs. 3 and 7; Fig. 3 shows a dielectric liner 305, i.e., dielectric spacer, which contacts a side surface 380, i.e., sidewall, of the second electrode 205-a and an outer segment of the second/top surface 310 of the OTS which is labeled 390).
Re: Claim 7, Pirovano discloses the memory device of Claim 6, and
wherein an outer sidewall of the dielectric spacer is vertically coincident with a sidewall of the ovonic threshold switching material portion and with a sidewall of the first electrode (Fig. 7 shows an embodiment 700-c wherein the dielectric spacer 305-d is vertically coincident with a sidewall of the memory component/OTS 220-e1 and a sidewall of the first electrode 210-e).
Re: Claim 9, Pirovano discloses the memory device of Claim 6, and further comprising:
an additional ovonic memory element that is laterally spaced from the ovonic memory element along a second horizontal direction that is perpendicular to a first horizontal direction and comprises an additional first electrode (Fig. 2 shows additional memory elements laterally spaced apart along a second direction perpendicular to a first horizontal direction with first electrodes 210),
an additional second electrode (Fig. 2 shows additional memory elements with a second electrodes 205), and
an additional ovonic threshold switching material portion located between the additional first electrode and the additional second electrode (Fig. 2: additional memory components laterally spaced apart with self-selecting memory component 220), wherein:
the first electrode and the second electrode have a same lateral extent along the second horizontal direction (See Fig. 2 for additional memory elements along a second horizontal direction; Fig. 7, 700-c shows a first and second electrode having a same lateral extent); and
the dielectric spacer contacts a sidewall of the additional second electrode and a segment of a surface of the additional ovonic threshold switching material portion (See Fig. 7, 700-b and 700-c; Fig. 7, 700-b shows a dielectric spacer 305-d contacting a sidewall of an additional second electrode and a segment of a surface of the additional OTS).
Re: Claim 11, Pirovano discloses the memory device of Claim 1, and
wherein the ovonic threshold switching material portion has a rectangular parallelepiped shape (¶0050: self-selecting memory component 220-a may be a rectangle; ¶0051: the cross-section of self-selecting memory component 220-a may be a trapezoid or an inverted trapezoid and illustrate a curved or slanted geometric profile... the cross-section of self-selecting memory component 220-a may be a trapezoid or an inverted trapezoid in the digit line direction and illustrate a tapered profile).
Re: Claim 12, Pirovano discloses the memory device of Claim 1 and
wherein the ovonic threshold switching material portion has a frustum shape or an inverted frustum shape (¶0051: the cross-section of self-selecting memory component 220-a may be a trapezoid or an inverted trapezoid and illustrate a curved or slanted geometric profile... the cross-section of self-selecting memory component 220-a may be a trapezoid or an inverted trapezoid in the digit line direction and illustrate a tapered profile).
Re: Claim 21, Pirovano discloses the memory device of Claim 1, wherein:
the first interface area is located at a first surface of the ovonic threshold switching material portion (Fig. 4: first interface area 315-a is located at a first/bottom surface of self-selecting memory component 220-b);
the second interface area is located at a second surface of the ovonic threshold switching material portion (Fig. 4: second interface area 310-a is located at a second/top surface of self-selecting memory component 220-b);
sidewalls of the ovonic threshold switching material portion are vertical (Fig. 4: sidewalls of self-selecting memory component 220-b are vertical); and
an area of the first surface of the ovonic threshold switching material portion and an area of the second surface of the ovonic threshold switching material portion are the same (Fig. 4: area of first and second surface of self-selecting memory component 220-b are the same).
Re: Claim 22, Pirovano discloses the memory device of Claim 1, and wherein:
the first interface area is located at a first surface of the ovonic threshold switching material portion (Fig. 4: first interface area 315-a is at a first surface of OTS 220-b);
the second interface area is located at a second surface of the ovonic threshold switching material portion (Fig. 4: second interface area 310-a is at a second surface of OTS 220-b);
the first surface of the ovonic threshold switching material portion is wider than the second surface of the ovonic threshold switching material portion (Fig. 4: first surface of OTS 220-b at 315-a is wider than the second surface at 310-a); and
a tapered surface of the ovonic threshold switching material portion continuously extends from the first electrode to the second electrode (Fig. 4: cross-section of OTS 220-b is a trapezoid or inverted trapezoid; ¶0051: the cross-section of self-selecting memory component 220-a may be a trapezoid or an inverted trapezoid).
Claims 13-15 and 24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by HSU et al. (US 20210296360 A1), hereinafter “Hsu.”
Re: Independent Claim 13, Hsu discloses a memory device (Fig. 8: 3D array 800), comprising:
a first alternating stack of first insulating rails and first electrically conductive rails (Note: Fig. 8 shows stacks along the Y-axis. Stacks are referenced from left to right along the Y-axis beginning with stack 1 on the left-most side of the Y-axis and ending with stack 4 on the right-most side of the Y-axis. Different stacks may be cited for convenience due to labeling in the figures (e.g., stack 2 shows transistors 812b and 812c which designate vertical sidewalls along the Z-axis for said stack); Fig. 8 shows a first alternating stack, see left-most stack along Y-axis, consisting of first electrically conductive rails 801a-f (shaded rails) and first insulating rails (not labeled, see unshaded insulating rails 807a-h for reference) above each electrically conductive rail; ¶0083: word line layers 801a-f, i.e., electrically conductive rails, and insulating layers 807a-h, i.e., insulating rails),
wherein the first insulating rails and the first electrically conductive rails extend along a first direction (Fig. 8: conductive and insulating rails extend along X-axis, i.e., first direction) and are interlaced along a second direction such that the first insulating rails and the first electrically conductive rails alternate along the second direction (Fig. 8: each stack has conductive and insulating rails which alternate along the Z-axis, i.e., second direction, and are interlaced), and
wherein the first alternating stack comprises a first surface and a second surface that are spaced from each other along a third direction that is perpendicular to the first direction and the second direction (Fig. 8: stack 2 shows a vertical surface with transistor 812-b, i.e., first surface, a vertical surface with transistor 812-c, i.e., second surface and wherein both surfaces are spaced apart along the Y-axis, i.e., third direction, which is perpendicular to both the first and second direction. Each of the four stacks in Fig. 8 have the same structural configuration. Therefore, the first stack also comprises two surfaces.),
the first surface containing first sidewalls of the first insulating rails and first sidewalls of the first electrically conductive rails (Fig. 8: first surface along 812-b of stack 2 contains first sidewalls of the insulating rails and electrically conductive rails) and located in a first vertical plane that is parallel to the first direction and to the second direction (Fig. 8 shows a transistor 812-b located on a first vertical surface which is in a vertical plane parallel to the X and Z axes, i.e., first and second directions, respectively);
a first ovonic memory strip comprising a first ovonic memory strip segment and a second ovonic memory strip segment (Fig. 8 shows a memory storage layer 805, i.e., first ovonic memory strip, which may consist of phase-change material such as chalcogenide, i.e., ovonic. First ovonic memory strip segment extends along the vertical surface of transistor 812-b and a second ovonic memory strip segment extends along the surface of transistor 812-c, i.e., first and second ovonic memory strip segments; ¶0084: 805... chalcogenide),
wherein the first ovonic memory strip segment extends along the second direction (Fig. 8: memory storage layer 805 extends along the Z-axis/second direction of transistor 812-b’s surface, i.e., first ovonic memory strip segment), the first sidewalls of the first insulating rails contact first surface segments of a first material having a first material composition in the first ovonic memory strip (Fig. 8: sidewalls of insulating rails contact segments of memory storage layer 805 along the vertical surface of 812-b, i.e., first surface segments of the first ovonic memory strip composed of chalcogen; ¶0084: 805... chalcogenide), and
the first sidewalls of the first electrically conductive rails contact second surface segments of said first material in the first ovonic memory strip (Fig. 8: sidewalls of electrically conductive rails 802 contact segments of memory storage layer 805 along the vertical surface of 812-b, i.e., second surface segments of the first ovonic memory strip composed of chalcogen; ¶0084: 805... chalcogenide), and
wherein the second ovonic memory strip segment extends along the second direction and contacts the second surface of the first alternating stack (Fig. 8: stack 2 shows a vertical surface with transistor 812-b, i.e., first surface, a vertical surface with transistor 812-c, i.e., second surface and wherein both surfaces are spaced apart along the Y-axis. Memory storage layer 805 extends along the Z-axis/second direction on the 812-c vertical surface and contacts the second surface, i.e., second surface of the alternating stack); and
a first conductive line comprising a first conductive line segment extending along the second direction and in contact with the first ovonic memory strip segment (Fig. 8: doped silicon layer 806-b, i.e., first conductive line segment, extends in the Z-axis/second direction along the 812-b-side surface and is in contact with the memory strip segment of 805 along 812-b, i.e., first ovonic memory strip segment; See ¶0087: The word line layers 801a-f and 802a-f form the gates of the transistors, and the silicon layers 806a, 806b, 806c, etc. form the channel regions of the transistors, i.e., conductive), and
further comprising a second conductive line segment extending along the second direction and in contact with the second ovonic memory strip segment (Fig. 8: doped silicon layer 806-c, i.e., second conductive line segment, extends along the Z-axis/second direction and is in contact with the memory strip segments of 805 along 812-c, i.e., second ovonic memory strip segment).
Re: Claim 14, Hsu discloses the memory device of Claim 13, and wherein:
the first ovonic memory strip segment and the second ovonic memory strip segment are connected to each other by a first connecting ovonic memory strip segment that extends along the third direction (Fig. 8 shows memory storage layer 805 which has a connecting strip at the top, extending along the Y-axis/third direction, which connects the first ovonic memory strip segment along 812-b and the second ovonic memory strip segment along 812-c); and
the first conductive line segment and the second conductive line segment are connected to each other by a first connecting conductive line segment that extends along the third direction (Fig. 8 shows doped silicon layer 806 which has a connecting strip at the top, extending along the Y-axis/third direction, which connects the first conductive line segment 806-b and the second conductive line segment 806-c).
Re: Claim 15, Hsu discloses the memory device of Claim 13, and
further comprising a second alternating stack of second insulating rails and second electrically conductive rails that is spaced from the first alternating stack along the third direction (Fig. 8 shows multiple stacks along the Y-axis/third direction),
wherein the second insulating rails and the second electrically conductive rails extend along the first direction and are interlaced along the second direction such that the second insulating rails and the second electrically conductive rails alternate along the second direction (See Fig. 8 which shows all four stacks having the same structure).
Re: Claim 24, Hsu discloses the memory device of Claim 14, and
wherein the first ovonic memory strip has a comb shape (See Figs. 8, 17, ¶0084: memory layer 805 wraps both sidewalls and the top of the word-line stack) comprising vertical tooth portions (See Figs. 8, 17 and ¶¶ 0083, 0086: layer 805 has vertical portions along Z on opposite sidewalls of stack 801a-f) connected to each other by a top horizontal connecting portion (See Figs. 8, 9, ¶ 0091: layer 805 extends across the top of the stack beneath contact 808b), and
the first ovonic memory strip segment and the second ovonic memory strip segment comprise respective ones of the vertical tooth portions (See Figs. 8, 17: first and second strip segments are the vertical portions of layer 805 on opposite sidewalls of the stack.).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8, 10 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over PIROVANO et al. (US 20190252606 A1) in view of YANG et al. (US 20220407000 A1), hereinafter “Yang.”
Re: Claim 8, Pirovano discloses the memory device of Claim 6, and wherein:
the first interface area is located at a first surface of the ovonic threshold switching material portion (Fig. 7 shows an embodiment 700-c wherein the first interface area is located between memory component/OTS 220-e and 210-e);
the first segment of the second surface of the ovonic threshold switching material portion comprises a center segment of the second surface of the ovonic threshold switching material portion (Fig. 7 shows an embodiment 700-c wherein a second surface between OTS 220-e and 205-e has a central segment, i.e., first segment, which is centered below 205-e);
the dielectric spacer laterally surrounds the second electrode and has a tubular configuration (Fig. 7 shows an embodiment 700-c with a dielectric spacer 305-d which surrounds the second electrode 205-e in a tubular configuration); and
the second segment of the second surface of the ovonic threshold switching material portion comprises an ... surface having a uniform lateral spacing between an inner periphery and an outer periphery (Fig. 7 shows an embodiment 700-c wherein a second surface of OTS, located between OTS 220-e and 205-e, has a second segment outside of the central segment, which has an annular surface and uniform lateral spacing between and inner and outer periphery; In other words, the second segment is underneath the dielectric spacer and has an annular shape surrounding 205-e).
However, Pirovano does not specifically disclose wherein the surface is ... annular.
In a similar field of endeavor, Yang discloses wherein the surface is ... annular (Fig. 1 shows encapsulation structure 120, i.e., dielectric, surrounding the cylindrical pillar including OTS material; ¶0024: pillar comprises a stack of materials having a side wall, such as a cylindrical side wall; ¶0045: pillar comprises a stack of materials having a side wall, such as a circular, oval or rectangular, cylindrical side wall).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application, to have modified the memory structure of Pirovano to have circular/cylindrically shaped memory pillars which are readily manufacturable for high density structures (See Yang, ¶0007).
Re: Claim 10, Pirovano discloses the memory device of Claim 1.
However, Pirovano does not specifically disclose wherein the ovonic threshold switching material portion has a cylindrical shape.
Yang further discloses wherein the ovonic threshold switching material portion has a cylindrical shape (See Fig. 1; ¶0024: pillar comprises a stack of materials having a side wall, such as a cylindrical side wall; ¶0045: pillar comprises a stack of materials having a side wall, such as a circular, oval or rectangular, cylindrical side wall).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application, to have modified the memory structure of Pirovano to have circular/cylindrically shaped memory pillars which are readily manufacturable for high density structures (See Yang, ¶0007).
Re: Claim 23, Pirovano discloses the memory device of Claim 8, and
wherein the dielectric spacer comprises an inner ... sidewall and an outer ... sidewall (Fig. 7, 700-c shows a dielectric spacer 305-d with an inner and outer sidewall), and
the uniform lateral spacing between the inner periphery and the outer periphery is a lateral thickness of the dielectric spacer between the inner ... sidewall and the outer ... sidewall (Fig. 7, 700-c shows a dielectric spacer 305-d having sidewalls with uniform lateral spacing between inner and outer periphery).
However, Pirovano does not specifically disclose wherein the sidewall is cylindrical.
In a similar field of endeavor, Yang discloses wherein the sidewall is cylindrical (See Fig. 1; ¶0024: pillar comprises a stack of materials having a side wall, such as a cylindrical side wall; ¶0045: pillar comprises a stack of materials having a side wall, such as a circular, oval or rectangular, cylindrical side wall).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application, to have modified the memory structure of Pirovano to have circular/cylindrically shaped memory pillars which are readily manufacturable for high density structures (See Yang, ¶0007).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over HSU et al. (US 20210296360 A1) in view of RABKIN et al. (US 9,818,801 B1), hereinafter “Rabkin.”
Re: Claim 16, Hsu discloses the memory device of Claim 13.
However, Hsu does not specifically disclose wherein the first ovonic memory strip comprises a stack of an ovonic threshold switching material strip comprising said first material and an electrode strip.
In a similar field of endeavor, Rabkin discloses wherein the first ovonic memory strip comprises a stack of an ovonic threshold switching material strip comprising said first material and an electrode strip (See col. 11, lns. 37-50; col. 12, lns. 19-30; col. 13, lns. 15-25; barrier layer 84 is formed directly on the sidewalls on the sidewalls of word lines 30 and insulating layers 60 and limits current at low fields while passing current at high fields, meeting applicant’s OTS definition.).
Hus teaches including a threshold-behavior selector with the memory element of Fig. 17 array (¶¶ 0082, 0107) but is silent on its implementation within the conformal memory layer 805. Rabkin teaches implementing the selector in an analogous vertical-bit-line resistive memory as a conformal barrier/conductive layer stack on the alternating-stack sidewalls, so that current is limited at low fields. Modifying Hsu’s memory layer 805 accordingly applies to a known technique to a known device ready for improvement, with predictable results (KSR; MPEP 2143(I)(C)-(D)).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM ADROVEL whose telephone number is (571)272-3048. The examiner can normally be reached 7:30 AM - 5:00 PM.
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/WILLIAM ADROVEL/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
