DETAILED ACTION
Election/Restrictions
Claims 17-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected method of forming a memory device, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 04/16/2026.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 11/01/2023 and 02/25/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Objections
Claim 13 is objected to because of the following informalities: line 10 of claim 13 states “containing the an ovonic memory element, …” contains a grammatical error.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 13-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by HSU (US 20200161371 A1), hereinafter “Hsu.”
Re: Claim 13, Hsu discloses a memory device (Fig. 3B: memory 304 and memory element 305; Also see Fig. 8H), comprising:
a first alternating stack of first insulating rails and first electrically conductive rails (Fig. 8H: first alternating stack of bit lines 801, i.e., electrically conductive rails, and insulator layers 802, i.e., insulating rails),
wherein the first insulating rails and the first electrically conductive rails extend along a first direction (Fig. 8H: 801 and 802 extend along a first direction, e.g., horizontal direction or X-axis), and are interlaced along a second direction such that the first insulating rails and the first electrically conductive rails alternate along the second direction (Fig. 8H: 801 and 802 are interlaced and extend in a second direction, e.g., vertical direction or Y-axis), and
wherein the first alternating stack comprises a first surface and a second surface that are spaced from each other along a third direction that is perpendicular to the first direction and the second direction (Fig. 8H: memory layer 807 surrounds each stack and has two vertical sides which create a first and second surface which are spaced apart in a third direction, e.g., direction orthogonal to X and Y axes, or Z-axis);
a first ovonic memory strip comprising a first ovonic memory strip segment containing the an ovonic memory element (Fig. memory element 305, i.e., memory strip; ¶0033: memory 304 that can be a resistive-switching material for RRAM, phase-change material such as chalcogenide, i.e., ovonic material; ¶0035: memory 304 is segmented, i.e., memory strip), the first ovonic memory strip segment extending along the second direction and in contact with the first surface of the first alternating stack (Fig. 3D: vertical cell structure 300A, extends along second direction, e.g., Y-axis, memory 304a in contact with selector 303 which is part of the memory layer 807, i.e., first surface), and
further comprising a second ovonic memory strip segment extending along the second direction and in contact with the second surface (Fig. 8H: memory layer 807 surrounds each stack and has two vertical sides which create a first and second surface; Fig. 8D: shows memory layer 807 which surrounds a stack and forms and a memory segment on each side of the selectors 806, i.e., second memory strip segment in contact with the second surface); and
a first conductive line comprising a first conductive line segment extending along the second direction and in contact with the first ovonic memory strip segment (Fig. 3B: selector 303a segment, i.e., first conductive line segment, extends in the vertical direction and in contact with memory segment), and
further comprising a second conductive line segment extending along the second direction and in contact with the second ovonic memory strip segment (Fig. 3B: selector 303b segment, i.e., second conductive line segment, extends in the vertical direction and in contact with memory segment).
Re: Claim 14, Hsu discloses the memory device of claim 13, and wherein:
the first ovonic memory strip segment and the second ovonic memory strip segment are connected to each other by a first connecting ovonic memory strip segment that extends along the third direction (Fig. 8H: memory layer 807 is continuous and surrounds a stack on both sides which connects the memory segments to each other. The memory layer wraps around the top of the stack wherein the top portion of memory layer 807 extends along the third direction, e.g., Z-axis); and
the first conductive line segment and the second conductive line segment are connected to each other by a first connecting conductive line segment that extends along the third direction (Fig. 8H: memory layer 807 wraps around the stack wherein the segment at the top, i.e., first connecting conductive line segment, of the stack connects the first and second conductive line segments. The top portion of the memory layer 807 extends along the third direction, e.g., Z-axis.).
Re: Claim 15, Hsu discloses the memory device of claim 13, and
further comprising a second alternating stack of second insulating rails and second electrically conductive rails that is spaced from the first alternating stack along the third direction (Fig. 8H: shows three stacks extending along the third direction, e.g., Z-axis),
wherein the second insulating rails and second electrically conductive rails extend along the second direction (Fig. 8H: center stack shows conductive rails 801 and insulating rails 802 extending along the second direction, e.g., Y-axis), and
are interlaced along the second direction such that the second insulating rails and the second electrically conductive rails alternate along the second direction (Fig. 8H: center stack Fig. 8H: center stack shows conductive rails 801 and insulating rails 802 interlaced and alternating along the second direction, e.g., Y-axis), and
wherein the second alternating stack comprises a third surface and a fourth surface that are spaced from each other along the third direction (Fig. 8H: center stack shows a memory layer 807 which wraps around the stack and thus creates a third and fourth surface that are space apart from each other in the third direction, e.g., Z-axis).
Re: Claim 16, Hsu discloses the memory device of claim 13, and wherein:
the first surface of the ovonic threshold switching material portion comprises an outer surface (Fig. 3B: memory 304 has an outer surface adjacent to bit line 302); and
the second surface of the ovonic threshold switching material portion comprises an inner surface (Fig. 3B: memory 304 has an inner surface adjacent to selector line 303a).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-12 are rejected under 35 U.S.C. 103 as being unpatentable over SUNG et al. (US 20230329007 A1, see IDS dated 02/25/2026), hereinafter “Sung,” in view of YANG et al. (US 20230263079 A1), hereinafter “Yang.”
Re: Claim 1, Sung discloses a memory device comprising an ovonic memory element (Fig. 1: memory cell 10, selection layer 12, i.e., ovonic memory element), wherein the ovonic memory element comprises:
a first electrode (Fig. 1: bottom electrode);
a second electrode (Fig. 1: top electrode); and
an ovonic threshold switching material portion located between the first electrode and the second electrode (Fig. 1: selection layer 12 between bottom and top electrodes; Also see Fig. 7; ¶0050: selection layer 12 may include a chalcogenide material having an ovonic threshold switch (OTS) characteristic),
wherein a first surface of the first electrode that contacts a first surface of the ovonic threshold switching material portion has a greater area than a first surface of the second electrode that contacts … a second surface of the ovonic threshold switching material portion (See Figs. 1 and 7; ¶0094: the memory cell 30 may have a structure in which the upper part of the memory cell 30 is wider than the lower part thereof or the lower part thereof is wider than the upper part thereof; In other words, the memory cell in Figs. 1 or 7 may have a tapered shape such that a first surface of a first electrode, i.e., bottom electrode, that is in contact with the selection layer 12 has a greater area than a first surface of the second electrode, i.e., top electrode, which has a smaller area that comes into contact with the selection layer 12 due to the tapered shape of the memory device).
However, Sung does not disclose … contacts a first segment of a second surface...
In a similar field of endeavor, Yang discloses … contacts a first segment of a second surface… (Fig. 22A: top electrode 507, i.e., second electrode, contacts a first segment of the top surface of a phase change element 506; a first surface of a bottom electrode, i.e., first electrode, 508 contacts a first surface of a phase change element 506).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date, to have modified the structure of Sung to include to include an oxygen-free spacer layer on the sides of the first segment as disclosed by Yang in order to mitigate oxidation and damage of the phase-change memory element (See Yang, ¶¶0093 and 0095).
Re: Claim 2, the combination of Sung in view of Yang discloses the memory device of claim 1.
Sung further discloses wherein the first surface of the first electrode has a greater lateral dimension along a first horizontal direction than the first surface of the second electrode (Fig. 1: memory cell 10 may have a tapered shape such that a first surface of a first electrode, e.g., bottom electrode of Figs. 1 or 7, has a greater lateral dimension, along a first horizontal direction, than a first surface of a second electrode, e.g., top electrode of Figs. 1 or 7; ¶0094: the memory cell 30 may have a structure in which the upper part of the memory cell 30 is wider than the lower part thereof or the lower part thereof is wider than the upper part thereof).
Re: Claim 3, the combination of Sung in view of Yang discloses the memory device of claim 1.
wherein the first electrode is located above the second electrode (Fig. 1: top electrode is located above bottom electrode; ¶0094: the memory cell 30 may have a structure in which the upper part of the memory cell 30 is wider than the lower part thereof or the lower part thereof is wider than the upper part thereof. In other words, a first electrode having a greater surface area at a surface may be located above a second electrode which has a smaller surface area at a surface.).
Re: Claim 4, the combination of Sung in view of Yang discloses the memory device of claim 3.
Sung further discloses wherein:
the first surface of the ovonic threshold switching material portion comprises a bottom surface (Claim Interpretation Note: Sung discloses in ¶0094 that “the memory cell 30 may have a structure in which the upper part of the memory cell 30 is wider than the lower part thereof or the lower part thereof is wider than the upper part thereof.” Therefore, selection layer 12 in Fig. 1 may have a wider lower part than the top part or vice versa.; Fig. 1: selection layer 12 has a bottom surface);
the second surface of the ovonic threshold switching material portion comprises a top surface (Fig. 1: selection layer 12 has a top surface, i.e., second surface);
the first surface of the first electrode comprises a top surface (Fig. 1: top electrode has a top surface above its first surface wherein the first surface is in contact with the top surface of selection layer 12); and
the first surface of the second electrode comprises a bottom surface (Fig. 1: bottom electrode has a bottom surface below its first surface wherein the first surface is in contact with the bottom surface of selection layer 12).
Re: Claim 5, the combination of Sung in view of Yang discloses the memory device of claim 3.
Sung further discloses wherein:
the first surface of the ovonic threshold switching material portion comprises a top surface (Fig. 1: selection layer 12 has a top surface, i.e., first surface of OTS, that is in contact with the bottom surface of the top electrode);
the second surface of the ovonic threshold switching material portion comprises a bottom surface (Fig. 1: selection layer 12 has a bottom surface, i.e., second surface of OTS, that is in contact with the top surface of the bottom electrode);
the first surface of the first electrode comprises a bottom surface (Fig. 1: top electrode has a bottom surface that is in contact with the top surface of selection layer 12); and
the first surface of the second electrode comprises a top surface (Fig. 1: bottom electrode has a top surface that is in contact with the bottom surface of selection layer 12).
Re: Claim 6, the combination of Sung in view of Yang discloses the memory device of claim 1.
Yang discloses further comprising a dielectric spacer contacting a sidewall of the second electrode and a second segment of the second surface of the ovonic threshold switching material portion (Fig. 22A: spacer layer 802, i.e., dielectric spacer, contacts sidewall of top electrode 507 and a second segment of second surface of phase-change element 506; ¶0094: oxygen-free spacer layer 802 over sidewalls of the phase-change element 506; ¶0095: oxygen-free spacer layer 802 may also include SiN, SiC, or SiCN).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date, to have modified the structure of Sung to include to include an oxygen-free spacer layer on the sides of the first segment as disclosed by Yang in order to mitigate oxidation and damage of the phase-change memory element (See Yang, ¶¶0093 and 0095).
Re: Claim 7, the combination of Sung in view of Yang discloses the memory device of claim 6.
Yang further discloses wherein an outer sidewall of the dielectric spacer is vertically coincident with a sidewall of the ovonic threshold switching material portion and with a sidewall of the first electrode (Fig. 22A: spacer layer 802 is vertically coincident with sidewall of phase-change element 506 and with sidewall of top electrode 507.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date, to have modified the structure of Sung to include to include an oxygen-free spacer layer on the sides of the first segment as disclosed by Yang in order to mitigate oxidation and damage of the phase-change memory element (See Yang, ¶¶0093 and 0095).
Re: Claim 8, the combination of Sung in view of Yang discloses the memory device of claim 6.
Yang further discloses wherein:
the first segment of the second surface of the ovonic threshold switching material portion comprises a center segment of the second surface of the ovonic threshold switching material portion (Fig. 22A: top center segment of phase-change element 506);
the dielectric spacer laterally surrounds the second electrode and has a tubular configuration (Fig. 22A: spacer layer 802); and
the second segment of the second surface of the ovonic threshold switching material portion comprises an annular surface having a uniform lateral spacing of at least 4 nm between an inner periphery and an outer periphery (¶0094: oxygen-free spacer layer 802 may have a thickness in a range from approximately 15 angstroms to approximately 40 angstroms and may correspond to approximately 100 angstroms of material etched from the oxygen-free patterned mask 510.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date, to have modified the structure of Sung to include to include an oxygen-free spacer layer on the sides of the first segment as disclosed by Yang in order to mitigate oxidation and damage of the phase-change memory element (See Yang, ¶¶0093 and 0095).
Re: Claim 9, the combination of Sung in view of Yang discloses the memory device of claim 6.
Yang also discloses further comprising:
an additional ovonic memory element that is laterally spaced from the ovonic memory element along a second horizontal direction and comprises an additional first electrode (See Fig. 22A),
an additional second electrode (See Fig. 22A), and
an additional ovonic threshold switching material portion located between the additional first electrode and the additional second electrode (See Fig. 22A);
the first electrode and the second electrode have a same lateral extent along the second horizontal direction (See Fig. 22A); and
the dielectric spacer contacts a sidewall of the additional second electrode and a segment of a top surface of the additional ovonic threshold switching material portion (See Fig. 22A. Please see citations provide in the previous claims.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date, to have modified the structure of Sung to include to include an oxygen-free spacer layer on the sides of the first segment as disclosed by Yang in order to mitigate oxidation and damage of the phase-change memory element (See Yang, ¶¶0093 and 0095).
Re: Claim 10, the combination of Sung in view of Yang discloses the memory device of claim 1.
Sung further discloses wherein the ovonic threshold switching material portion has a cylindrical shape (¶0093: cylindrical shape).
Re: Claim 11, the combination of Sung in view of Yang discloses the memory device of claim 1.
Sung further discloses wherein the ovonic threshold switching material portion has a rectangular shape (¶0093: memory cell 30 may have a square or polygonal pillar shape, i.e., rectangular shape).
Re: Claim 12, the combination of Sung in view of Yang discloses the memory device of claim 1.
Sung further discloses wherein the ovonic threshold switching material portion has a frustum shape or an inverted frustum shape (¶0093: memory cell 30 may have a tapered or polygonal shape, i.e., frustum; ¶0094: the memory cell 30 may have a structure in which the upper part of the memory cell 30 is wider than the lower part thereof or the lower part thereof is wider than the upper part thereof, i.e., inverted frustum shape).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
CHOI et al. (US 10,026,478 B1) – Fig. 3B is relevant to claims 13-16
YABE (US 11,158,384 B1) – Figs. 4C and 4E are relevant to claims 13-16
YANG et al. (US 20220407000 A1) – Figs. 1-6 are relevant to claims 1-12
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM ADROVEL whose telephone number is (571)272-3048. The examiner can normally be reached 7:30 AM - 5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LEONARD CHANG can be reached at (571) 270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM ADROVEL/ Examiner, Art Unit 2898
/Leonard Chang/
Supervisory Patent Examiner, Art Unit 2898
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