DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Species 3 (figure 3) in the reply filed on January 7, 2026 is acknowledged.
Information Disclosure Statement
The references cited within the IDS documents have been considered.
IDS document dates: January 3, 2024; January 23, 2024; October 31, 2024.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 6-12, 15, and 20-26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mun et al. (US 2022/0165658 A1, hereinafter referred to as ‘Mun’).
As to claim 1, Mun teaches an assembly, comprising:
a substrate (186) having a major surface;
inter-metal dielectric (IMD) layers (e.g. 126, 128, 132) above the major surface of the substrate;
metal layers (e.g. 130, 142, 148) between the respective IMD layers;
a capacitor (300) having first and second plates (110, 162), wherein the first plate (162) comprises a first metal region in a first one of the metal layers and at least one metal BEOL (see par. 0003) interconnect (166) located in a first one of the IMD layers and connected to the first metal region. See figure 1.
As to claim 6, Mun teaches the capacitor structure, as noted above in the rejection of claim 1. Therefore, since Mun teaches the same structure as claimed by the applicant, the capacitor structure of Mun necessarily has an impedance of the capacitor is formed by the first metal region and the at least one metal BEOL interconnect.
As to claim 7, Mun teaches the first plate (162) comprises a second metal region (160) in a second one of the metal layers and at least one metal BEOL interconnect (188) located in a second one of the IMD layers and connected to the second metal region, wherein the first and second metal regions and the BEOL interconnects in the first and second ones of the IMD layers are electrically connected. See figure 1.
As to claim 8, Mun teaches a shallow trench isolation layer (118) on the substrate aligned with capacitor. See figure 1; see para. 0014.
As to claim 9, Mun teaches the capacitor has a symmetrical shape. See figure 1. The applicant defines symmetrical shape in the specification as “the first and second plates are located in different ones of the metal layers and are vertically aligned with respect to the major surface of the substrate” which is taught by Mun.
As to claim 10, Mun teaches the first and second plates (110, 162) are located in different ones of the metal layers and are vertically aligned with respect to the major surface of the substrate. See figure 1.
As to claim 11, Mun teaches a conductive path (through 116) from an uppermost surface of the assembly to the second plate through interconnects in the IMD layers and metal regions in the metal layers. See figure 1.
As to claim 12, Mun teaches the capacitor structure, as noted above in the rejection of claim 1. Therefore, since Mun teaches the same structure as claimed by the applicant, the capacitor structure of Mun necessarily also teaches the first plate is configured for high voltage and the second plate is configured for low voltage.
As to claim 15, Mun teaches a method to firm an assembly, comprising:
providing a substrate (186) having a major surface;
forming inter-metal dielectric (IMD) layers (e.g. 126, 128, 132) above the major surface of the substrate;
forming metal layers (e.g. 130, 142, 148) between the respective IMD layers;
forming a capacitor (300) having first and second plates (110, 162), wherein the first plate (162) comprises a first metal region in a first one of the metal layers and at least one metal BEOL (see par. 0003) interconnect (166) located in a first one of the IMD layers and connected to the first metal region. See figure 1.
As to claim 20, Mun teaches the capacitor structure, as noted above in the rejection of claim 15. Therefore, since Mun teaches the same structure as claimed by the applicant, the capacitor structure of Mun necessarily has an impedance of the capacitor is formed by the first metal region and the at least one metal BEOL interconnect.
As to claim 21, Mun teaches the first plate (162) comprises a second metal region (160) in a second one of the metal layers and at least one metal BEOL interconnect (188) located in a second one of the IMD layers and connected to the second metal region, wherein the first and second metal regions and the BEOL interconnects in the first and second ones of the IMD layers are electrically connected. See figure 1.
As to claim 22, Mun teaches including forming a shallow trench isolation layer (118) on the substrate aligned with capacitor. See figure 1; see para. 0014.
As to claim 23, Mun teaches the capacitor has a symmetrical shape. See figure 1. The applicant defines symmetrical shape in the specification as “the first and second plates are located in different ones of the metal layers and are vertically aligned with respect to the major surface of the substrate” which is taught by Mun.
As to claim 24, Mun teaches the first and second plates (110, 162) are located in different ones of the metal layers and are vertically aligned with respect to the major surface of the substrate. See figure 1.
As to claim 25, Mun teaches a conductive path (through 116) from an uppermost surface of the assembly to the second plate through interconnects in the IMD layers and metal regions in the metal layers. See figure 1.
As to claim 26, Mun teaches the capacitor structure, as noted above in the rejection of claim 1. Therefore, since Mun teaches the same structure as claimed by the applicant, the capacitor structure of Mun necessarily also teaches the first plate is configured for high voltage and the second plate is configured for low voltage.
Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: see the attached form PTO-892 for pertinent cited art.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Scott B. Geyer (telephone: 571-272-1958). The examiner can normally be reached on Monday to Friday, 10AM - 4PM (ET). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at: http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim (telephone: 571-272-8458). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only.
For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (in U.S.A. or Canada) or 571-272-1000.
/SCOTT B GEYER/ Primary Examiner, Art Unit 2812
Prosecution Insights