DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The previously presented claim(s) 1-20 have been considered.
Response to Arguments
Applicant’s arguments, see Remarks, pages 6-14, filed 04/14/2026, with respect to the rejection(s) of claim(s) 1-7, and 9-20 under 35 U.S.C. 102(a)(1) and claim 8 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of TSAI.
Regarding Independent Claim(s) 1, 9, and 17. The Applicant argues (see Remarks, pages 7-13) that KIM fails to disclose or suggest the limitation or feature of claims 1, 9, and 17, recites, “wherein the thermal via vertically overlaps the semiconductor die.” The Examiner agrees that the arguments are persuasive and therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made as mentioned in the above paragraph. For instance, the prior-art of TSAI teaches, a semiconductor package structure (Fig. 10A, 300, antenna package), comprising: a substrate (Fig. 10A, 201, carrier substrate) having a wiring structure (Fig. 10A, 210, redistribution structure); a semiconductor die (Fig. 10A, 220, semiconductor device) disposed over the substrate (Fig. 10A, 201, carrier substrate) and electrically coupled ([0112]) to the wiring structure (Fig. 10A, 210, redistribution structure); a molding material (Fig. 10A, 302) surrounding the semiconductor die (Fig. 10A, 220, semiconductor device); an interposer disposed (Fig. 10A, 120, antenna structure) over the semiconductor die (Fig. 10A, 220, semiconductor device); and a thermal via (Fig. 10A, 106) disposed in the interposer (Fig. 10A, 120, antenna structure) and extending to a bottom surface of the interposer (Fig. 10A, 120, antenna structure), wherein the thermal via vertically overlaps (Fig. 10A, 106) the semiconductor die (Fig. 10A, 220, semiconductor device).
Regarding Claim(s) 2-8, 10-16, and 18-20: The dependent claims 2-8, 10-16, and 18-20 follow similar arguments as Claim 1, upon further consideration, a new-grounds of rejection is made based on the prior-art mentioned above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-7, and 9-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Po-Hao Tsai et al, (hereinafter TSAI), US 20230223364 A1, in view of Jongyoun Kim et al, (hereinafter KIM), US 20220310496 A1, (prior art used in the previous Office Action filed on 01/20/2026).
Regarding Claim 1, TSAI teaches a semiconductor package structure (Fig. 10A, 300, antenna package), comprising:
a substrate (Fig. 10A, 201, carrier substrate) having a wiring structure (Fig. 10A, 210, redistribution structure);
a semiconductor die (Fig. 10A, 220, semiconductor device) disposed over the substrate (Fig. 10A, 201, carrier substrate) and electrically coupled ([0112]) to the wiring structure (Fig. 10A, 210, redistribution structure);
a molding material (Fig. 10A, 302) surrounding the semiconductor die (Fig. 10A, 220, semiconductor device);
an interposer disposed (Fig. 10A, 120, antenna structure) over the semiconductor die (Fig. 10A, 220, semiconductor device); and
a thermal via (Fig. 10A, 106) disposed in the interposer (Fig. 10A, 120, antenna structure) and extending to a bottom surface (annotated Figure 10A) of the interposer (Fig. 10A, 120, antenna structure), wherein the thermal via (Fig. 10A, 106) vertically overlaps (annotated Figure 10A) the semiconductor die (Fig. 10A, 220, semiconductor device).
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Though TSAI teaches a semiconductor package structure comprising antenna structure (120) as equated to interposer that is disposed over the semiconductor device (220), TSAI does not disclose a semiconductor package structure comprising: an interposer disposed over the semiconductor die.
KIM teaches a semiconductor package structure (Fig. 5, 4), comprising: an interposer (Fig. 5, 600, upper redistribution layer) disposed over the semiconductor die (Fig. 5, 210A/210B, lower semiconductor chip).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified TSAI to incorporate the teachings of KIM, such that the semiconductor package structure comprising: a semiconductor package structure comprising: an interposer disposed over the semiconductor die, so that the upper redistribution layer (600), may include an upper redistribution patters (620), and/or upper redistribution pads (640), and electrically connected to both the conductive structures (410) of the connection substrate (400), and the conductive terminal (650) of the upper package (20) (KIM, [0128]).
Regarding Claim 2, TSAI as modified by KIM teaches the semiconductor package structure as claimed in claim 1.
TSAI further teaches the semiconductor package structure (Fig. 10A, 300, antenna package), wherein the thermal via (Fig. 10A, 106) comprises metal, polymer, or a combination thereof (Fig. 10A, some conductive material may be formed over an end of a thermal vias, 106, [0026]).
Regarding Claim 3, TSAI as modified by KIM teaches the semiconductor package structure as claimed in claim 1.
TSAI further teaches the semiconductor package structure (Fig. 10A, 300, antenna package), further comprising a thermal interface material (Fig. 10B, 304, thermal adhesive layer, may be a material such as thermal interface materials (TIM), [0059]) connecting the thermal via (Fig. 10B, 106) and the semiconductor die (Fig. 10B, 220, semiconductor device) and surrounded by the molding material (Fig. 10B, 302).
Regarding Claim 4, TSAI as modified by KIM teaches the semiconductor package structure as claimed in claim 3.
TSAI further teaches the semiconductor package structure (Fig. 10A, 300, antenna package), wherein the thermal interface material (Fig. 10B, 304, thermal adhesive layer, may be a material such as thermal interface materials (TIM), [0059]) comprises metal, polymer, or a combination thereof (Fig. 10B, the thermal adhesive layer, 304 may be a material such as thermal conductivity polymer films, silver pastes, thermal interface materials (TIM), graphene, the like, or a combination, [0059]).
Regarding Claim 5, TSAI as modified by KIM teaches the semiconductor package structure as claimed in claim 4.
TSAI further teaches the semiconductor package structure (Fig. 10A, 300, antenna package), wherein the thermal via (Fig. 10B, 106) and the thermal interface material (Fig. 10B, 304, thermal adhesive layer, may be a material such as thermal interface materials (TIM), [0059]) comprise a same material (thermal vias, 106 made of conductive material [0026], thermal adhesive layers, 304 made of thermal conductive polymer films, silver pastes, [0059]).
Regarding Claim 6, TSAI as modified by KIM teaches the semiconductor package structure as claimed in claim 4.
TSAI further teaches the semiconductor package structure (Fig. 10A, 300, antenna package), further comprising a plurality of conductive structures (Fig. 10B, 214, conductive pillars) electrically coupling (Fig. 10B, 118, connectors) the interposer (Fig. 10B, 120, antenna structure) to the substrate (Fig. 10B, 201, carrier substrate) on opposite sides (opposite side of 304) of the semiconductor die (Fig. 10B, 220, semiconductor device) and surrounded by the molding material (Fig. 10B, 302).
Regarding Claim 7, TSAI as modified by KIM teaches the semiconductor package structure as claimed in claim 6.
TSAI further teaches the semiconductor package structure (Fig. 10A, 300, antenna package), wherein the interposer (Figs. 1-2/12, 400, antenna structure) comprises a conductive layer (Figs. 1-2/12, 102, conductive layers, [0066]) coupling the thermal via (Fig. 17, 106) to one of the conductive structures (Fig. 21, 118/802/214, connector/bonding pads/conductive pillars).
Regarding Claim 9, TSAI teaches a semiconductor package structure (Fig. 10A, 300, antenna package), comprising:
a first redistribution layer (Fig. 10A, 210, redistribution structure);
a semiconductor die (Fig. 10A, 220, semiconductor device) disposed over the first redistribution layer (Fig. 10A, 210, redistribution structure);
a second redistribution layer (Fig. 10A, 120, antenna structure) disposed over the semiconductor die (Fig. 10A, 220, semiconductor device); and
a thermal via (Fig. 10A, 106) disposed in the second redistribution layer (Fig. 10A, 120, antenna structure) and extending to a bottom surface (annotated Figure 10A) of the second redistribution layer (Fig. 10A, 120, antenna structure), wherein the thermal via (Fig. 10A, 106) vertically overlaps (annotated Figure 10A) the semiconductor die (Fig. 10A, 220, semiconductor device).
Though TSAI teaches a semiconductor package structure comprising an antenna structure (120) as equated to a second distribution layer that is disposed over the semiconductor device (220), TSAI does not disclose a semiconductor package structure comprising: a second redistribution layer disposed over the semiconductor die.
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KIM teaches a semiconductor package structure (Fig. 5, 4), comprising: a second redistribution layer (Fig. 5, 600, upper redistribution layer) disposed over the semiconductor die (Fig. 5, 210A/210B, lower semiconductor chip).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified TSAI to incorporate the teachings of KIM, such that the semiconductor package structure comprising: a semiconductor package structure comprising: a second redistribution layer disposed over the semiconductor die, so that the upper redistribution layer (600), may include an upper redistribution patters (620), and/or upper redistribution pads (640), and electrically connected to both the conductive structures (410) of the connection substrate (400), and the conductive terminal (650) of the upper package (20) (KIM, [0128]).
Regarding Claim 10, TSAI as modified by KIM teaches the semiconductor package structure as claimed in claim 9.
TSAI further teaches the semiconductor package structure (Fig. 10A, 300, antenna package), further comprising a thermal interface material (Fig. 10B, 304, thermal adhesive layer, may be a material such as thermal interface materials (TIM), [0059]) in contact with the thermal via (Fig. 10B, 106) and the semiconductor die (Fig. 10B, 220, semiconductor device).
Regarding Claim 11, TSAI as modified by KIM teaches the semiconductor package structure as claimed in claim 10.
TSAI further teaches the semiconductor package structure (Fig. 10A, 300, antenna package), wherein the thermal interface material (Fig. 10B, 304, thermal adhesive layer, may be a material such as thermal interface materials (TIM), [0059]) comprises metal, polymer, or a combination thereof (Fig. 10B, the thermal adhesive layer, 304 may be a material such as thermal conductivity polymer films, silver pastes, thermal interface materials (TIM), graphene, the like, or a combination, [0059]).
Regarding Claim 12, TSAI as modified by KIM teaches the semiconductor package structure as claimed in claim 10.
TSAI further teaches the semiconductor package structure (Fig. 10A, 300, antenna package), wherein the thermal via (Fig. 10B, 106) and the thermal interface material (Fig. 10B, 304, thermal adhesive layer, may be a material such as thermal interface materials (TIM), [0059]) comprise a same material (thermal vias, 106 made of conductive material [0026], thermal adhesive layers, 304 made of thermal conductive polymer films, silver pastes, [0059]).
Regarding Claim 13, TSAI as modified by KIM teaches the semiconductor package structure as claimed in claim 10.
TSAI further teaches the semiconductor package structure (Fig. 10A, 300, antenna package), wherein a sidewall (annotated Figure 10B) of the thermal interface material (Fig. 10B, 304, thermal adhesive layer, may be a material such as thermal interface materials (TIM), [0059]) is substantially aligned (annotated Figure 10B) with a sidewall (annotated Figure 10B) of the semiconductor die (Fig. 10B, 220, semiconductor device).
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Regarding Claim 14, TSAI as modified by KIM teaches the semiconductor package structure as claimed in claim 9.
TSAI further teaches the semiconductor package structure (Fig. 10A, 300, antenna package), wherein the thermal via (Fig. 10B, 106) is in contact with a backside (annotated Figure 10B) of the semiconductor die (Fig. 10B, 220, semiconductor device).
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Regarding Claim 15, TSAI as modified by KIM teaches the semiconductor package structure as claimed in claim 9.
TSAI further teaches the semiconductor package structure (Fig. 10A, 300, antenna package), further comprising a plurality of conductive pillars (Fig. 10B, 214, conductive pillars) between the second redistribution layer (Fig. 10A, 120, antenna structure) and the first redistribution layer (Fig. 10A, 210, redistribution structure).
Regarding Claim 16, TSAI as modified by KIM teaches the semiconductor package structure as claimed in claim 6.
TSAI further teaches the semiconductor package structure (Fig. 10A, 300, antenna package), wherein the second redistribution layer (Figs. 1-2/12, 400, antenna structure) comprises a conductive layer (Figs. 1-2/12, 102, conductive layers, [0066]) coupling the thermal via (Fig. 17, 106) to one of the conductive pillars (Fig. 21, 118/802/214, connector/bonding pads/conductive pillars).
Regarding Claim 17, TSAI teaches a semiconductor package structure (Fig. 10A, 300, antenna package), comprising:
a first redistribution layer (Fig. 10A, 210, redistribution structure);
a semiconductor die (Fig. 10A, 220, semiconductor device) disposed over the first redistribution layer (Fig. 10A, 210, redistribution structure);
a bump structure electrically (Figs. 9A/10A, 221/222, contact pads/external connectors may be a conductive bumps (or microbumps), [0054]) coupling the semiconductor die (Figs. 9A/10A, 220, semiconductor device) to the first redistribution layer (Figs. 9A/10A, 210, redistribution structure);
a second redistribution layer (Fig. 10A, 120, antenna structure) disposed over the semiconductor die (Fig. 10A, 220, semiconductor device); and
a plurality of thermal vias (Fig. 10A, 106) embedded in the second redistribution layer (Fig. 10A, 120, antenna structure) and extending to a bottom surface (annotated Figure 10A) of the second redistribution layer (Fig. 10A, 120, antenna structure) and in contact with the semiconductor die (Fig. 10A, 220, semiconductor device).
Though TSAI teaches a semiconductor package structure comprising an antenna structure (120) as equated to a second distribution layer that is disposed over the semiconductor device (220), TSAI does not disclose a semiconductor package structure comprising: a second redistribution layer disposed over the semiconductor die.
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KIM teaches a semiconductor package structure (Fig. 5, 4), comprising: a second redistribution layer (Fig. 5, 600, upper redistribution layer) disposed over the semiconductor die (Fig. 5, 210A/210B, lower semiconductor chip).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified TSAI to incorporate the teachings of KIM, such that the semiconductor package structure comprising: a semiconductor package structure comprising: a second redistribution layer disposed over the semiconductor die, so that the upper redistribution layer (600), may include an upper redistribution patters (620), and/or upper redistribution pads (640), and electrically connected to both the conductive structures (410) of the connection substrate (400), and the conductive terminal (650) of the upper package (20) (KIM, [0128]).
Regarding Claim 18, TSAI as modified by KIM teaches the semiconductor package structure as claimed in claim 17.
TSAI further teaches the semiconductor package structure (Fig. 10A, 300, antenna package), wherein the thermal vias (Fig. 10A, 106) comprise metal, polymer, or a combination thereof (Fig. 10A, some conductive material may be formed over an end of a thermal vias, 106, [0026]).
Regarding Claim 19, TSAI as modified by KIM teaches the semiconductor package structure as claimed in claim 17.
TSAI further teaches the semiconductor package structure (Fig. 10A, 300, antenna package), further comprising a conductive pillar (Fig. 21, 118/802/214, connector/bonding pads/conductive pillars) adjacent to the semiconductor die (Fig. 21, 220, semiconductor device) and coupled to one of the thermal vias (Fig. 17, 106) through a conductive layer (Figs. 1-2/12, 102, conductive layers, [0066]) of the second redistribution layer (Figs. 1-2/12, 400, antenna structure).
Regarding Claim 20 TSAI as modified by KIM teaches the semiconductor package structure as claimed in claim 19.
TSAI further teaches the semiconductor package structure (Fig. 10A, 300, antenna package), further comprising a molding material (Fig. 10B, 302) surrounding the semiconductor die (Fig. 10B, 220, semiconductor device), the bump structure (Figs. 9A/10A, 221/222, contact pads/external connectors may be a conductive bumps (or microbumps), [0054]), and the conductive pillar (Fig. 21, 118/802/214, connector/bonding pads/conductive pillars).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over TSAI in view of KIM as applied to claim(s) 1-7, and 9-20 above and furtherin view of Marshall Maple et al, (hereinafter MAPLE), US 20170018478 A1 (prior art used in the previous Office Action filed on 01/20/2026).
Regarding Claim 8, TSAI as modified by KIM teaches the semiconductor package structure as claimed in claim 1.
TSAI as modified by KIM does not explicitly disclose the semiconductor package structure, wherein a width of the thermal via increases in a direction toward the semiconductor die.
MAPLE teaches the semiconductor package structure (Fig. 2, 200), wherein a width of the thermal via (Fig. 2, 212/214/216) increases ([0056]) in a direction (Fig. 2, Z-direction) toward the semiconductor die (Fig. 2, 223).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have TSAI as modified by KIM to incorporate the teachings of MAPLE, such that the semiconductor package structure, wherein a width of the thermal via increases in a direction toward the semiconductor die, so that heat follows the shape of the pluralities of vias for an improved thermal dissipation in a semiconductor package structure (MAPLE, [0057], [0002]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20220272828 A1 – Figure 9
STATEMENT OF RELEVANCE – A cross-sectional view of a component carrier, wherein the conductive layer structure, (via type) 104, overlaps an electronic component, 108.
US 20230148220 A1 – Figure 14F
STATEMENT OF RELEVANCE – A cross-sectional view of a die assembly, 1002 wherein the contact holes, 1032 and interconnections, 1444 overlaps the die, 1026.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SESHA SAIRAMAN SRINIVASAN whose telephone number is (703)756-1389. The examiner can normally be reached Monday-Friday 7:30 AM -5:30 PM.
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
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