DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
No Information Disclosure Statement has been filed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-7, and 9-20 and is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jongyoun Kim et al, (hereinafter KIM), US 20220310496 A1.
Regarding Claim 1, KIM teaches a semiconductor package structure (Fig. 5, 4), comprising:
a substrate (Fig. 5, 100, redistribution substrate) having a wiring structure (Fig. 5, 110W, first wiring part of the first redistribution pattern, 110, [0034]);
a semiconductor die (Fig. 5, 210A/210B, lower semiconductor chip) disposed over the substrate (Fig. 5, 100, redistribution substrate) and electrically coupled (Fig. 5, 250A/250B, lower solder bumps) to the wiring structure (Fig. 5, 110W, first wiring part of the first redistribution pattern, 110, [0034]);
a molding material (Fig. 5, 300, molding layer) surrounding the semiconductor die (Fig. 5, 210A/210B, lower semiconductor chip);
an interposer (annotated Figure 5, “wiring part”, [0128]) disposed over the semiconductor die (Fig. 5, 210A/210B, lower semiconductor chip); and
a thermal via (annotated Figure 5, “via part”, [0128]) disposed in the interposer (annotated Figure 5) and extending to a bottom surface of the interposer (annotated Figure 5, “wiring part”, [0128]), wherein the thermal via (annotated Figure 5, “via part”, [0128]) vertically overlaps (annotated Figure 5) the semiconductor die (Fig. 5, 210A/210B, lower semiconductor chip).
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Regarding Claim 2, KIM teaches the semiconductor package structure (Fig. 5, 4) as claimed in claim 1, wherein the thermal via comprises metal, polymer, or a combination thereof (Fig. 5, 620, the upper redistributions patterns may include metal, such as copper; each or one or more of the upper redistribution patterns, 620 may include a “via part”, [0128]).
Regarding Claim 3, KIM teaches the semiconductor package structure (Fig. 5, 4) as claimed in claim 1, further comprising a thermal interface material (Fig. 5, 890, the thermal radiation structure may include a heat sink, a heat slug or a thermal interface material (TIM) layer, [0056]) connecting (annotated Figure 5) the thermal via (annotated Figure 5, “via part”, [0128]) and the semiconductor die (Fig. 5, 210A/210B, lower semiconductor chip) and surrounded by the molding material (Fig. 5, 300, molding layer).
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Regarding Claim 4, KIM teaches the semiconductor package structure (Fig. 5, 4) as claimed in claim 3, wherein the thermal interface material (Fig. 5, 890, the thermal radiation structure may include a heat sink, a heat slug or a thermal interface material (TIM) layer, [0056]) comprises metal, polymer, or a combination thereof (Fig. 5, 890, thermal radiation structure, 890 may include a thermal interface material (TIM) and may include metal such as copper, [0119]).
Regarding Claim 5, KIM teaches the semiconductor package structure (Fig. 5, 4) as claimed in claim 4, wherein the thermal via (Fig. 5, 620, the upper redistributions patterns may include metal, such as copper; each or one or more of the upper redistribution patterns, 620 may include a “via part”, [0128]) and the thermal interface material (Fig. 5, 890, the thermal radiation structure may include a heat sink, a heat slug or a thermal interface material (TIM) layer, [0056]) comprise a same material (metal, copper, [0128]. [0119]).
Regarding Claim 6, KIM teaches the semiconductor package structure (Fig. 5, 4) as claimed in claim 1, further comprising a plurality of conductive structures (Fig. 5, 410) electrically coupling the interposer (annotated Figure 5, “wiring part”, [0128]) to the substrate (Fig. 5, 100/710, redistribution substrate/upper substrate) on opposite sides (annotated Figure 5) of the semiconductor die (Fig. 5, 210/A/210B/720, lower semiconductor chip/upper semiconductor chip) and surrounded by the molding material (Fig. 5, 300/730, molding layer/upper molding layer).
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Regarding Claim 7, KIM teaches the semiconductor package structure (Fig. 5, 4) as claimed in claim 6, wherein the interposer (annotated Figure 5, “wiring part”, [0128]) comprises a conductive layer (Fig. 5, 620 upper redistribution patterns) coupling the thermal via (annotated Figure 5, “via part”, [0128]) to one of the conductive structures (Fig. 5, 410).
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Regarding Claim 9, KIM teaches a semiconductor package structure (Fig. 5, 4), comprising:
a first redistribution layer (Fig. 5, 100, redistribution substrate);
a semiconductor die (Fig. 5, 210A/210B, lower semiconductor chip) disposed over the first redistribution layer (Fig. 5, 100, redistribution substrate);
a second redistribution layer (Fig. 5, 600, upper redistribution layer) disposed over the semiconductor die (Fig. 4, 210A/210B, lower semiconductor chip); and
a thermal via (annotated Figure 5, “via part”, [0128]) disposed in the second redistribution layer (Fig. 5, 600, upper redistribution layer) and extending to a bottom surface (annotated Figure 5) of the second redistribution layer (Fig. 5, 600, upper redistribution layer), wherein the thermal via (annotated Figure 5, “via part”, [0128]) vertically overlaps (annotated Figure 5) the semiconductor die (Fig. 5, 210A/210B, lower semiconductor chip).
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Regarding Claim 10, KIM teaches the semiconductor package structure (Fig. 5, 4) as claimed in claim 9, further comprising a thermal interface material (Fig. 5, 890, the thermal radiation structure may include a heat sink, a heat slug or a thermal interface material (TIM) layer, [0056]) in contact with the thermal via (annotated Figure 5, “via part”, [0128]) and the semiconductor die (Fig. 5, 210A/210B, lower semiconductor chip).
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Regarding Claim 11, KIM teaches the semiconductor package structure (Fig. 5, 4) as claimed in claim 10, wherein the thermal interface material (Fig. 5, 890, the thermal radiation structure may include a heat sink, a heat slug or a thermal interface material (TIM) layer, [0056]) comprises metal, polymer, or a combination thereof (Fig. 5, 890, thermal radiation structure, 890 may include a thermal interface material (TIM) and may include metal such as copper, [0119]).
Regarding Claim 12, KIM teaches the semiconductor package structure (Fig. 5, 4) as claimed in claim 10, wherein the thermal via (Fig. 5, 620, the upper redistributions patterns may include metal, such as copper; each or one or more of the upper redistribution patterns, 620 may include a “via part”, [0128]) and the thermal interface material (Fig. 5, 890, the thermal radiation structure may include a heat sink, a heat slug or a thermal interface material (TIM) layer, [0056]) comprise a same material (metal, copper, [0128]. [0119]).
Regarding Claim 13, KIM teaches the semiconductor package structure (Fig. 5, 4) as claimed in claim 10, wherein a sidewall (annotated Figure 5) of the thermal interface material (Fig. 5, 890, the thermal radiation structure may include a heat sink, a heat slug or a thermal interface material (TIM) layer, [0056]) is substantially aligned (annotated Figure 5) with a sidewall (annotated Figure 5) of the semiconductor die (Fig. 5, 210A/210B, lower semiconductor chip).
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Regarding Claim 14, KIM teaches the semiconductor package structure (Fig. 5, 4) as claimed in claim 9, wherein the thermal via (annotated Figure 5, “via part”, [0128]) is in contact with a backside (annotated Figure 5) of the semiconductor die (Fig. 5, 210A/210B, lower semiconductor chip). (NOTE: The backside of the semiconductor die is considered similar to the instant application, paragraph, [0059] and Figure 4B, wherein the backside of the semiconductor die is closer to the thermal interface material).
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Regarding Claim 15, KIM teaches the semiconductor package structure (Fig. 5, 4) as claimed in claim 9, further comprising a plurality of conductive pillars (Fig. 5, 410, conductive structures) between the second redistribution layer (Fig. 5, 600, upper redistribution layer) and the first redistribution layer (Fig. 5, 100, redistribution substrate).
Regarding Claim 16, KIM teaches the semiconductor package structure (Fig. 5, 4) as claimed in claim 15, wherein the second redistribution layer (Fig. 5, 600, upper redistribution layer) comprises a conductive layer (Fig. 5, 620, the upper redistributions patterns) coupling the thermal via (Fig. 5, 620, the upper redistributions patterns may include metal, such as copper; each or one or more of the upper redistribution patterns, 620 may include a “via part”, [0128]) to one of the conductive pillars (Fig. 5, 410, conductive structures).
Regarding Claim 17, KIM teaches a semiconductor package structure (Fig. 5, 4), comprising:
a first redistribution layer (Fig. 5, 100, redistribution substrate);
a semiconductor die (Fig. 5, 210A/210B, lower semiconductor chip) disposed over the first redistribution layer (Fig. 5, 100, redistribution substrate);
a bump structure electrically (Fig. 5, 250A/250B, lower solder bumps) coupling the semiconductor die (Fig. 5, 210A/210B, lower semiconductor chip) to the first redistribution layer (Fig. 5, 100, redistribution substrate);
a second redistribution layer (Fig. 5, 600, upper redistribution layer) disposed over the semiconductor die (Fig. 5, 210A/210B, lower semiconductor chip); and
a plurality of thermal vias (annotated Figure 5, “via part”, [0128]) embedded in the second redistribution layer (Fig. 5, 600, upper redistribution layer) and in contact (annotated Figure 5) with the semiconductor die (Fig. 5, 210A/210B, lower semiconductor chip).
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Regarding Claim 18, KIM teaches the semiconductor package structure (Fig. 5, 4) as claimed in claim 17, wherein the thermal vias comprise metal, polymer, or a combination thereof (Fig. 5, 620, the upper redistributions patterns may include metal, such as copper; each or one or more of the upper redistribution patterns, 620 may include a “via part”, [0128]).
Regarding Claim 19, KIM teaches the semiconductor package structure (Fig. 5, 4) as claimed in claim 17, further comprising a conductive pillar (Fig. 5, 410, conductive structures) adjacent to the semiconductor die (Fig. 5, 210A/210B, lower semiconductor chip) and coupled to one of the thermal vias (annotated Figure 5, “via part”, [0128]) through a conductive layer (Fig. 5, 620, the upper redistributions patterns) of the second redistribution layer (Fig. 5, 600, upper redistribution layer).
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Regarding Claim 20, KIM teaches the semiconductor package structure (Fig. 5, 4) as claimed in claim 19, further comprising a molding material (Fig. 5, 300, molding layer) surrounding the semiconductor die (Fig. 5, 210A/210B, lower semiconductor chip), the conductive structure, and the conductive pillar (Fig. 5, 410, plurality of conductive structures; may be a pillar, [0126]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over KIM in view of Marshall Maple et al, (hereinafter MAPLE), US 20170018478 A1.
Regarding Claim 8, KIM teaches the semiconductor package structure as claimed in claim 1.
KIM does not explicitly disclose the semiconductor package structure, wherein a width of the thermal via increases in a direction toward the semiconductor die.
MAPLE teaches the semiconductor package structure (Fig. 2, 200), wherein a width of the thermal via (Fig. 2, 212/214/216) increases ([0056]) in a direction (Fig. 2, Z-direction) toward the semiconductor die (Fig. 2, 223).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified KIM to incorporate the teachings of MAPLE, such that the semiconductor package structure, wherein a width of the thermal via increases in a direction toward the semiconductor die, so that heat follows the shape of the pluralities of vias for an improved thermal dissipation in a semiconductor package structure (MAPLE, [0057], [0002]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20230060720 A1 – Figure 6L
STATEMENT OF RELEVANCE – Method of fabricating a semiconductor package with redistribution circuit structure.
US 20230245947 A1 – Figure 6, [0034]
STATEMENT OF RELEVANCE – Heat dissipating unit include Thermal Interfacing Material (TIM).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SESHA SAIRAMAN SRINIVASAN whose telephone number is (703)756-1389. The examiner can normally be reached Monday-Friday 7:30 AM -5:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812