DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A in the reply filed on May 19, 2026 is acknowledged.
Claims 4-5 and 9 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on May 19, 2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 6, the claim recites the limitation "the bottom portion" in line 8. There is insufficient antecedent basis for this limitation in the claim. For purposes of Examination, Examiner will interpret this to read as “…located below
Claims 7-8 are also rejected as they are dependent on claim 6.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 and 6-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Karda et. al. (US 20210066298 A1), hereinafter Karda.
Regarding claim 1, Karda teaches a memory cell structure (Fig 7 memory device 600, [0066]), comprising: a vertical bit line (Fig 7 bit lines 621, [0068]); a first semiconductor layer (Fig 7 material 720, [0092]) surrounding a first portion (Fig 7 portion of material 720 surrounding 621) of the vertical bit line (Fig 7 bit lines 621, [0068]); a first gate (Fig 7 conductive region 741T, [0079]) surrounding (Fig 7 741T surrounds the material 720; [0103] discloses 741T can span across material 720) the first semiconductor layer (Fig 7 material 720, [0092]) ; a second semiconductor layer (Fig 7 portion 710, [0100]) surrounding a second portion (Fig 7 portion of portion 710 surrounding 621) of the vertical bit line (Fig 7 bit lines 621, [0068]); a gate dielectric layer (Fig 7 dielectric 718, [0083]) surrounding a third portion (Fig 7 portion of dielectric 718 surrounding 621) of the vertical bit line (Fig 7 bit lines 621, [0068]), wherein the gate dielectric layer (Fig 7 dielectric 718, [0083]) separates the first semiconductor layer (Fig 7 material 720, [0092]) and the first gate (Fig 7 conductive region 741T, [0079]) from the second semiconductor layer (Fig 7 portion 710, [0100]).
Regarding claim 2, Karda teaches the first gate (Fig 7 conductive region 741T, [0079]) is coupled to ([0079] discloses 741T and 741B are electrically coupled; [0104] discloses the spanning allows line 741 control of both transistors T1 and T2) the second semiconductor layer (Fig 7 portion 710, [0100]) to form a first channel region.
The recitation calling for forming a first channel does not distinguish over the cited reference regardless of the function allegedly performed by the claimed device, because only the device per se is relevant, no matter which of the device’s functions is referred to in the claim, and if the prior art structure is capable of performing the intended function, then it meets the claim. In re Casey, 152 USPQ 235 (CCPA 1967). In the instant application, when a transistor is turned on a channel is formed.
Regarding claim 3, Karda teaches a second gate (Fig 7 conductive region 741B, [0079]) coupled to ([0079] discloses 741T and 741B are electrically coupled; [0104] discloses the spanning allows line 741 control of both transistors T1 and T2) the first semiconductor layer (Fig 7 material 720, [0092]) to form a second channel region.
The recitation calling for forming a second channel does not distinguish over the cited reference regardless of the function allegedly performed by the claimed device, because only the device per se is relevant, no matter which of the device’s functions is referred to in the claim, and if the prior art structure is capable of performing the intended function, then it meets the claim. In re Casey, 152 USPQ 235 (CCPA 1967). In the instant application, when a transistor is turned on a channel is formed.
Regarding claim 6, Karda teaches a memory cell structure (Fig 7 memory device 600, [0066]), comprising: a vertical bit line (Fig 7 bit lines 621, [0068]); a first semiconductor layer (Fig 7 material 720, [0092]) surrounding a first portion (Fig 7 portion of material 720 surrounding 621) of the vertical bit line (Fig 7 bit lines 621, [0068]); a first gate (Fig 7 conductive region 741T, [0079]) surrounding (Fig 7 741T surrounds the material 720; [0103] discloses 741T can span across material 720) the first semiconductor layer (Fig 7 material 720, [0092]) ; a gate dielectric layer (Fig 7 dielectric 718, [0083]) surrounding (Fig 7 dielectric 718 surrounds the first semiconductor layer and first gate in the vertical direction) the first semiconductor layer (Fig 7 material 720, [0092]) and the first gate (Fig 7 conductive region 741T, [0079]); and a second semiconductor layer (Fig 7 portion 710, [0100]) surrounding a second portion (Fig 7 portion of portion 710 surrounding 621) of the vertical bit line (Fig 7 bit lines 621, [0068]) and located below the bottom portion (Fig 7 portion 710 is below the bottom portion of dielectric 718) of the gate dielectric layer (Fig 7 dielectric 718, [0083]).
Regarding claim 7, Karda teaches the first gate (Fig 7 conductive region 741T, [0079]) is coupled to ([0079] discloses 741T and 741B are electrically coupled; [0104] discloses the spanning allows line 741 control of both transistors T1 and T2) the second semiconductor layer (Fig 7 portion 710, [0100]) to form a first channel region.
The recitation calling for forming a first channel does not distinguish over the cited reference regardless of the function allegedly performed by the claimed device, because only the device per se is relevant, no matter which of the device’s functions is referred to in the claim, and if the prior art structure is capable of performing the intended function, then it meets the claim. In re Casey, 152 USPQ 235 (CCPA 1967). In the instant application, when a transistor is turned on a channel is formed.
Regarding claim 8, Karda teaches a second gate (Fig 7 conductive region 741B, [0079]) coupled to ([0079] discloses 741T and 741B are electrically coupled; [0104] discloses the spanning allows line 741 control of both transistors T1 and T2) the first semiconductor layer (Fig 7 material 720, [0092]) to form a second channel region.
The recitation calling for forming a second channel does not distinguish over the cited reference regardless of the function allegedly performed by the claimed device, because only the device per se is relevant, no matter which of the device’s functions is referred to in the claim, and if the prior art structure is capable of performing the intended function, then it meets the claim. In re Casey, 152 USPQ 235 (CCPA 1967). In the instant application, when a transistor is turned on a channel is formed.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ding et. al. (WO 2023197753 A1) teaches a 2T0C memory device that has vertically stacked transistors.
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and Figures may apply.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALVIN L LEE whose telephone number is (703)756-1921. The examiner can normally be reached Monday - Friday 8:30 am - 5 pm (ET).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, STEVEN GAUTHIER can be reached at (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALVIN L LEE/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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