Continued Examination under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/24/2025 has been entered.
DETAILED ACTION
This non-final action is responsive to communications: RCE filed on 12/24/2025.
In the response filed, applicant amended claims 1, 6, and 8-9; no other claims are added or, cancelled. Claims 1-20 are pending. Claims 1 and 10 are independent.
Examiner Notes
A) Per MPEP 2111 and 2111.01, claims are given their broadest reasonable interpretation without importing limitations from spec B) Per MPEP 2173.04: “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. C). Per MPEP 2141.02 VI prior art must be considered in its entirety. D) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103 and once reference teaching product appearing to be substantially identical is made the basis of a rejection, and examiner presents evidence or reasoning tending to show inherency, the burden of proof shifts to the applicant.
Notice of Pre-AIA or AIA Status
3. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant is requested to check all claim informality, language issues (e.g. antecedent issues, redundant limitation issues, grammar, spelling, typo issues etc.) for all claims (if applicable) to expedite prosecution since informality scrutiny in this office action is not exhaustive and applicant’s co-operation is sought in this regard.
Claim Interpretation (invoking 35 U.S.C. §112(f))
4. This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are apparatus claim 1:
1) “data clock signal” using a driven states “…first voltage level for a first time period and toggles during a second time period… feedback data is variable based on the first voltage level…” to perform apparatus functions (claim 1, lines 4-7).
The term "data clock signal" in the limitation (1) above is a generic placeholder that is not preceded by a structural modifier that drives the signal. For instance, none of the modifiers of “data clock signal” recites structure to perform the function(s) to store the signal state.
Because the limitation(s) above are being interpreted under 35 U.S.C. 112(f), they are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. However, the specification does not appear to set forth corresponding structure(s) for the recited functions “…first voltage level for a first time period and toggles during a second time period…” (claim 1, lines 4-5).
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
5. The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL. — The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
6. Claims 1-9 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention.
Apparatus claim 1 fail to comply with the written description requirement,
because the claim recites limitations (1) above (see Claim Construction Section in this Office action) without having adequate support for corresponding structure(s) in the specification as these claim limitations invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (see Claim Interpretation above as set forth in this Office action). As such, claim 1 recite functions that have no limits and covers every conceivable means for achieving the stated function in each of the limitations (1) above. That is, the Applicant fails to provide corresponding structure or acts that one of ordinary skill in the art would be able to determine its structural or functional equivalence. Without being able to determine this, how would one of ordinary skill in the art have the requisite notice that to infringe on the claim. Disclosure Fig. 2-Fig. 5B, para [0043], para [0044], [0050], para [0064] teaches preceding voltage level and toggled states of the data clock. See also, Fig. 6-Fig. 20 where data clock signal states are used to perform functions. Specially the preceding voltage level is set and controlled which requires driver or, special circuitry. It is not clear what circuitry uses data clock signal to achieve signal states and Figures 2- 20 fails to show any circuitry besides showing only signals states and associated functions. Spec fails to show any specific hardware associated with controlling/ setting the data clock signal states. Therefore, limitation (1) invokes the scrutiny of interpretation under 35 U.S.C. 112(f) and requires that the Applicant affirmatively disclaim that the Applicant wishes to be limited to particular corresponding structure(s) in the written description or amend the claim to falls outside of scrutiny of interpretation under 35 U.S.C. 112(f). Accordingly, the disclosure is not commensurate with the scope of the claims.
All dependent claims inclusive of claims 1-9 are rejected under the same category.
7. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. — The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
8. Claims 1-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant(s) regard as their invention.
Here, the independent claim 1 is indefinite, because it is unclear what
corresponding structure(s) for performing the entire claimed function in the limitation (1) above (see Claim Interpretation section above) are as the written description fails to clearly disclose or link the corresponding structure to the entire claimed function. Limitations (1) invokes the scrutiny of interpretation under 35 U.S.C. 112(f) and requires that the Applicant affirmatively disclaim that the Applicant wishes to be limited to particular corresponding structure(s) in the written description or amend the claim to falls outside of scrutiny of interpretation under 35 U.S.C. 112(f). Spec fails to show any specific hardware associated with the functions. Disclosure Fig. 2-Fig. 5B, para [0043], para [0044], [0050], para [0064] teaches preceding voltage level and toggled states of the data clock. See also, Fig. 6-Fig. 20 where data clock signal states are used to perform functions. Specially the preceding voltage level is set and controlled which requires driver or, special circuitry. It is not clear what circuitry uses data clock signal to achieve signal states and Figures 2- 20 fails to show any circuitry besides showing only signals states and associated functions. Spec fails to show any specific hardware associated with controlling/ setting the data clock signal states. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
All dependent claims inclusive of claims 1-9 are rejected under the same category.
The Applicant can amend:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
Or
The Applicant can affirmatively disclaim:
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01 (o) and 2181.
Claim Rejections - 35 USC § 102
9. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
10. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
11. Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gans (US 2020/0162066 A1).
Regarding independent claim 1, Gans teaches a memory device (Fig. 3: 306) communicating with a memory controller (Fig. 3: 302), the memory device comprising:
a divide circuit (Fig. 3: 357 “divider”) configured to generate an internal data clock signal (para [0038], Fig. 3: iWCKn) based on a data clock signal (Fig. 3: WCK_t, WCK_c),
wherein the data clock signal has a first voltage level for a first time period (Fig. 5: WCK constant level prior to t0 time period) and toggles during a second time period consecutive to the first time period (Fig. 5: WCK toggles during t0-t3 time period);
a detect circuit (Fig. 3: 358 “driver”) configured to generate a feedback data (Fig. 3: RDQS) based on the internal data clock signal (Fig. 3: based on iWCKn input),
wherein the feedback data (Fig. 3: RDQS) is variable based on the first voltage level (RDQS is generated by adjusting iWCKn voltage and/or current. para [0042] teaches “…iWCKn clock signals may pass through a driver 358, which may modulate the iWCKn clock signals…e.g., by increasing a voltage and/or current of the signals…”); and
an input/output circuit (Fig. 3: 344 signal transmission circuitry associated with “RDQS clock path”) configured to output the feedback data (Fig. 3: RDQS) to the memory controller (Fig. 3: 302. See also para [0016]).
Claim Rejections - 35 USC § 103
12. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
13. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
14. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
15. Claims 1, and 3 is/are rejected under 35 U.S.C. 103 as being obvious over Satoh (US 2019/0181847 A1), in view of Chang et al. (US 2023/0029968 A1).
Regarding independent claim 1, Satoh teaches a memory device communicating with a memory controller (“memory device 100” and “memory controller”. See e.g., para [0013], Fig. 1-Fig. 5),
the memory device comprising:
a divide circuit (Fig. 3: 310) configured to generate an internal data clock signal (Fig. 3: LCLK 2ET, LCLK 2EB, LCLK 2OT, LCLK 2OB) based on a data clock signal (Fig. 3: LCLK),
wherein the data clock signal (Fig. 2, Fig. 3: LCLK) has a first voltage level for a first time period (para [0023]: initial LCLK with ICLK level prior to phase and duty cycle adjustment) and toggles during a second time period (para [0023], Fig. 6A: LCLK toggling shown after phase and duty cycle adjustment) consecutive to the first time period;
a detect circuit (Fig. 3: 330) configured to generate a feedback data (Fig. 3: DCE which is based on HF, LF) based on the internal data clock signal (Fig. 3: LCLK 2ET, LCLK 2EB, LCLK 2OT, LCLK 2OB),
wherein the feedback data is variable based on the first voltage level (para [0032]: “duty cycle error” information which is based on input ICLK level prior to phase, duty cycle adjustment. See Fig. 3: DCE signal).
Satoh is silent with respect to an input/output circuit configured to output the feedback data to the memory controller.
Chang teaches -
a detect circuit (Fig. 7: 465, 457) configured to generate a feedback data (para [0104], Fig. 7: MT_INF “monitoring information”) based on the internal data clock signal (Fig. 7: ACLKI, ACLKIB, ACLKQ, ACLKQB),
wherein the feedback data (Fig. 7: MT_INF) is variable based on the first voltage level (Fig. 7: initial CCLKI with WCK level).
an input/output circuit (Fig. 7: 475, 467) configured to output the feedback data to the memory controller (para [0106]: “…MT_INF…to memory controller 100…”. See also Fig. 1 duty controller in memory controller).
Satoh and Chang are in the same field of endeavor of DRAM clock offset, skew, duty improvement and they are in analogous field of art.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine Chang’s teaching into the teachings of Satoh such that input/output circuit can be employed to output feedback data to memory controller in order to have capability “…correcting phase skews of multi-phase clock signals while training a duty or duty cycle of a data clock signal…” and thus improve operation speed (Chang para [0005]).
Regarding claim 3, Satoh and Chang teach the memory device of claim 1. Satoh and Chang does not explicitly teach a frequency of the internal data clock signal is half of a frequency of the data clock signal. However, Satoh does disclose the internal data clock signals (Fig. 3: LCLK 2ET, LCLK 2EB, LCLK 2OT, LCLK 2OB) are double the clock period of the data clock signal (Fig. 3: LCLK), and that “other multipliers may be used” (see Satoh para. 27).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use half the frequency of the internal data clock signal with respect to the data clock signal, since Satoh discloses that multiple data clock division multipliers may be used, suggesting that the operation of the device would not change.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-9 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Prior Art Not Relied Upon
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure: Penney (US 10,256,795 B1): Penney teaches a method to prevent meta-stability in a memory device comprising a four-phase generator (col. 1, lines 8-10: “…methods to mitigate metastability effects in clocking signals...” see Fig. 7: 350, Fig. 5: 250 and associated circuitry components can be combined to be used as clocking signal circuit of Fig. 1: 10 device that “…prevent metastability…”). All figures are applicable. Zerbe (US 2006/0120409 A1): Fig. 1-Fig. 44 applicable.
KIM (US 2023/0005515 A1: Fig. 1-Fig. 12 applicable.
It is suggested that applicant consider all prior arts made of record.
Allowable Subject Matter
Claims 10-20 are indicated as allowable.
Regarding claims listed above, the prior art of record does not appear to teach, suggest, or provide motivation for combination for the limitations of the claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUSHFIQUE SIDDIQUE whose telephone number is (571)270-0424. The examiner can normally be reached 7:00 am-4:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander George Sofocleous can be reached on (571) 272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825
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