Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of group I in the reply filed on 02/24/26 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 10-17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Oh et al., US 2020/0227398.
Oh et al. shows the invention as claimed including a memory device comprising:
A first structure (C in fig. 13 or CW in fig. 16) having a plurality of planes (210 in fig. 13) and a pad part (see paragraph 0148) between two planes adjacent to each other among the plurality of planes (IR which comprises PAD1 is between plane regions PR1 and PR2 in fig. 16), each of the plurality of planes including a memory cell; and
A second structure (P in fig. 13 or PW in fig. 16) bonded to the first structure, the second structure including a peripheral circuit, wherein the plurality of planes are minimum units in which operations are independently performed (see paragraphs 0140-0141), the plurality of planes are in an n x m array having rows and columns, n and m independently are integers of 2 or larger (2x2 in fig. 13), and the pad part (IR in fig. 16 and 18) is between the rows of the n x m array, the columns of the n x m array, or both the rows of the n x m array and the columns of the n x m array.
With respect to dependent claim 10, note that Oh et al. discloses a memory device wherein the columns of the plurality of planes extend in a first direction, the rows of the plurality of planes extend in a second direction, and the pad part includes a first pad part between two planes arranged in the first direction and a second pad part between two planes arranged in the second direction (see, for example, figs. 13/16).
Concerning dependent claim 11, note that Oh et al. discloses wherein at least one of the first pad part and the second pad part is connected to the memory cell of a corresponding plane among the plurality of planes, the peripheral circuit, or both the peripheral circuit and the memory cell of the corresponding plane (again, see figs. 13/16).
Regarding dependent claim 12, Oh et al. discloses wherein the first structure is one of a plurality of first structures in the memory device, the second structure is one of a plurality of second structures in the memory device, the memory device includes two or more memory chips stacked on each other to provide stacked memory chips; and each memory chip of the two or more memory chips is constituted by a corresponding one of the plurality of first structures and a corresponding one of the plurality of second structures stacked on each other (see particularly figs. 13-16).
Concerning dependent claim 13, note that the claims are directed to the product and therefore the method of formation is not given patentable weight unless it materially affects the product.
With respect to dependent claim 14, the pad part further includes a bypass pad part passing through one of the stacked memory chips and electrically connecting memory chips that are not adjacent to each other (see, for example, paragraph 0148).
Regarding dependent claim 15, Oh et al. discloses wherein the stacked memory chips include three or more memory chips stacked on each other and at least some memory chips in the stacked memory chips are connected through the bypass part (see paragraph 0148).
With respect to dependent claim 16, note that the pad part further includes a through-via penetrating the first structure and connected to the peripheral circuit (see fig. 16).
As to dependent claim 17, note that in Oh et al. the first structure is one of a plurality of first structures; and the plurality of first structures are sequentially stacked on the second structure and directly bonded to the second structure (see figs. 13 and 16).
Allowable Subject Matter
Claims 2-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art, either singly or in combination, particularly Oh et al., US 2020/0227398, fails to anticipate or render obvious, the following limitations in combination with the other claimed limitations: the pad part includes a first signal pad on the second surface of the first structure and a second signal pad on the second surface of the second structure, as required by dependent claim 2.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2007/0206419 discloses a multiple plane memory device (see abstract).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD A BOOTH whose telephone number is (571)272-1668. The examiner can normally be reached Monday to Friday, 8:30 to 5:00.
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/RICHARD A BOOTH/ Primary Examiner, Art Unit 2812
May 29, 2026
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