DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 2 Modification 2 in the reply filed on 04 March 2026 is acknowledged. Applicant submits that claims 1, 3, 4, and 5 are readable thereon and claim 1 is generic. Examiner has considered the claim language and will treat claims 1-6 and 9-10 on the merits as being readable upon the elected Species 2 and Modification 2, wherein claims 7-8 are withdrawn from consideration. The restriction is maintained, and any subsequent amendments to the claims reading on the non-elected species will be withdrawn from future consideration in view of the election (ELC. of 04 March 2026).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 5, 6, 9, and 10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Bo Yu et al. (US 2024/0096782 A1; hereinafter Yu).
Regarding Claim 1, Yu discloses a semiconductor device (Fig. 1 and Fig. 3) comprising:
a plurality of lead frames (11/21; ¶0079);
a plurality of semiconductor elements (3/4; ¶0088) mounted to the plurality of lead frames (11/21);
a heat sink (13/23; thermally conductive; ¶0082) disposed below the plurality of lead frames (11/21); and
an insulating sheet (12/22; ¶0078) interposed between the plurality of lead frames (11/21) and the heat sink (13/23) (as shown in Fig. 1), wherein
the insulating sheet (12/22) and the heat sink (13/23) are each divided into two or more portions (insulating sheet is divided into portion 12 and portion 22; heat sink is divided into portion 13 and portion 23), and
all the plurality of semiconductor elements (3/4) are arranged at positions overlapping the insulating sheet (12/22) and the heat sink (13/23) in plan view (as shown in Fig. 1 and Fig. 3).
Regarding Claim 2, Yu discloses the semiconductor device according to claim 1, wherein the two or more portions of the insulating sheet (12 and 22) have different thermal conductivities (Yu; ¶0078; “A thermal conductivity of the first insulation layer 12 is higher than a thermal conductivity of the second insulation layer 22”).
Regarding Claim 5, Yu discloses the semiconductor device according to claim 1, wherein the two or more portions of the insulating sheet (12/22) have shapes (quadrilateral shape) corresponding to arrangement of the plurality of lead frames (using the broadest reasonable interpretation of the claim language of “corresponding to arrangement”; the quadrilateral shapes of the portions of the insulating sheet 12 and 22 corresponds to and overlaps with the arrangement of the lead frames 11 and 21; as shown in Fig. 1 and Fig. 3).
Regarding Claim 6, Yu discloses the semiconductor device according to claim 2, wherein the two or more portions of the insulating sheet (12/22) have shapes (quadrilateral shape) corresponding to arrangement of the plurality of lead frames (using the broadest reasonable interpretation of the claim language of “corresponding to arrangement”; the quadrilateral shapes of the portions of the insulating sheet 12 and 22 corresponds to and overlaps with the arrangement of the lead frames 11 and 21; as shown in Fig. 1 and Fig. 3).
Regarding Claim 9, Yu discloses the semiconductor device according to claim 1, wherein the two or more portions of the insulating sheet (12/22) are asymmetrically arranged in plan view (as shown in Fig. 3; 1 and 2 (which comprise 12 and 22, respectively) are arranged asymmetrically in plan view).
Regarding Claim 10, Yu discloses the semiconductor device according to claim 2, wherein the two or more portions of the insulating sheet (12/22) are asymmetrically arranged in plan view (as shown in Fig. 3; 1 and 2 (which comprise 12 and 22, respectively) are arranged asymmetrically in plan view).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Vikas Gupta et al. (US 20240112978 A1; hereinafter Gupta).
Regarding Claim 3, Yu discloses the semiconductor device according to claim 1, wherein two or more semiconductor elements (4) are arranged on one portion of the insulating sheet (22) (and discloses in ¶0079 that the semiconductor element 4 may be alternatively connected to or not connected to a corresponding “line layer” which is the lead frame).
However, Yu is silent regarding wherein two or more lead frames (21) are in intimate contact with the one portion of the insulating sheet (22).
In the same field of endeavor, Gupta teaches a similar semiconductor device in Fig. 1; comprising a plurality of electronic components (30; equivalent to semiconductor elements; ¶0025) disposed on a plurality of lead frames (Fig. 1; 21, 21A, 21A; which electrically connect to 30; ¶0029), an insulating sheet with two portions (10’ and 10; ¶0025), and a heat sink with two portions (22 left and 22 right divided by G1; which dissipates heat from element 30 in a direction D1; as described in ¶0029); wherein the two portions are asymmetrically arranged (as shown in Fig. 1; wherein the left portion includes one element 30 and the right portion includes two elements 30 and is asymmetrically shaped accordingly), wherein two or more lead frames (21A, 21A; on the right side of G1) of the two or more electronic elements (30, 30; on the right side of G1) are in intimate contact with one portion of the insulating sheet (the one portion 10; on the right side of G1).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the two or more lead frames supporting the two or more electronic elements in intimate contact with the one asymmetrically larger portion of the insulating sheet (of Gupta) in the device of Yu in order to electrically connect both similar electronic elements while providing appropriate heat dissipation paths (Gupta; ¶0029-¶0030) for the respective asymmetric portions (wherein both Yu and Gupta teach asymmetrical arrangements for the plurality of semiconductor elements in respective Fig. 1) while assigning the optimal thermal conductivity to respective circuits to manage device cost (Yu; ¶0079).
Regarding Claim 4, Yu discloses the semiconductor device according to claim 2, wherein two or more semiconductor elements (4) are arranged on one portion of the insulating sheet (22) (and discloses in ¶0079 that the semiconductor element 4 may be alternatively connected to or not connected to a corresponding “line layer” which is the lead frame).
However, Yu is silent regarding wherein two or more lead frames (21) are in intimate contact with the one portion of the insulating sheet (22).
In the same field of endeavor, Gupta teaches a similar semiconductor device in Fig. 1; comprising a plurality of electronic components (30; equivalent to semiconductor elements; ¶0025) disposed on a plurality of lead frames (Fig. 1; 21, 21A, 21A; which electrically connect to 30; ¶0029), an insulating sheet with two portions (10’ and 10; ¶0025), and a heat sink with two portions (22 left and 22 right divided by G1; which dissipates heat from element 30 in a direction D1; as described in ¶0029); wherein the two portions are asymmetrically arranged (as shown in Fig. 1; wherein the left portion includes one element 30 and the right portion includes two elements 30 and is asymmetrically shaped accordingly), wherein two or more lead frames (21A, 21A; on the right side of G1) of the two or more electronic elements (30, 30; on the right side of G1) are in intimate contact with one portion of the insulating sheet (the one portion 10; on the right side of G1).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the two or more lead frames supporting the two or more electronic elements in intimate contact with the one asymmetrically larger portion of the insulating sheet (of Gupta) in the device of Yu in order to electrically connect both similar electronic elements while providing appropriate heat dissipation paths (Gupta; ¶0029-¶0030) for the respective asymmetric portions (wherein both Yu and Gupta teach asymmetrical arrangements for the plurality of semiconductor elements in respective Fig. 1) while assigning the optimal thermal conductivity to respective circuits to manage device cost (Yu; ¶0079).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN PRIDEMORE whose telephone number is (703)756-4640. The examiner can normally be reached Monday - Friday 8:00am - 4:00pm EST.
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NATHAN PRIDEMORE
Examiner
Art Unit 2898
/NATHAN PRIDEMORE/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898