DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments/amendments, see Remarks/Claims, filed 10 July 2026, with respect to the rejection(s) of the claim(s) under 35 USC §102 in the previous Office action have been fully considered and are persuasive. Specifically, the prior art of the previous rejection does not expressly disclose “the lead frames each include leads extending outside of the molding resin” as recited in amended claim 1. Therefore, the previous rejection has been withdrawn. However, upon further search and consideration, a new ground(s) of rejection is made in view of Yu (of record) in view of newly discovered reference Keitaro Ichikawa et al. (US 2016/0233151 A1), as presented in detail below. Claims 7-8 remain withdrawn from consideration.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5-6, and 9-15 are rejected under 35 U.S.C. 103 as being unpatentable over Bo Yu et al. (US 2024/0096782 A1; hereinafter Yu) in view of Keitaro Ichikawa et al. (US 2016/0233151 A1; hereinafter Ichikawa).
Regarding Claim 1, Yu discloses a semiconductor device (Fig. 1 and Fig. 3) comprising:
a plurality of lead frames (11/21; ¶0079; copper ¶0081);
a plurality of semiconductor elements (3/4; ¶0088) mounted to the plurality of lead frames (11/21);
a heat sink (13/23; thermally conductive; ¶0082) disposed below the plurality of lead frames (11/21); and
an insulating sheet (12/22; ¶0078) interposed between the plurality of lead frames (11/21) and the heat sink (13/23) (as shown in Fig. 1); and
a molding resin (5; ¶0092) partially sealing the lead frames (11/21) (Fig. 1), wherein
the insulating sheet (12/22) and the heat sink (13/23) are each divided into two or more portions (insulating sheet is divided into portion 12 and portion 22; heat sink is divided into portion 13 and portion 23),
all the plurality of semiconductor elements (3/4) are arranged at positions overlapping the insulating sheet (12/22) and the heat sink (13/23) in plan view (as shown in Fig. 1 and Fig. 3).
Yu does not expressly disclose wherein the lead frames each include leads extending outside of the molding resin.
In the same field of endeavor, Ichikawa teaches a similar semiconductor device (Fig. 1 and Fig. 2) comprising a plurality of lead frames (1a+1c, 1b+1d ; ¶0024; which is made of the same copper material as the lead frames of Yu) with semiconductor elements (2, 3 ; ¶0024) mounted thereon (respectively), and an insulating sheet (6; ¶0024) positionally between the lead frames and a heat sink (7; ¶0032), a molding resin (8; ¶0024) partially sealing the lead frames (1a+1c and 1b+1d), wherein the lead frames each include leads (1c and 1d) extending outside the molding resin (8) (as shown in Fig. 1 and Fig. 2).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the disclosures of Ichikawa (above) and Yu in order to provide electrical connection to the outside (Ichikawa; ¶0033).
Regarding Claim 2, modified Yu discloses the semiconductor device according to claim 1, wherein the two or more portions of the insulating sheet (12 and 22) have different thermal conductivities (Yu; ¶0078; “A thermal conductivity of the first insulation layer 12 is higher than a thermal conductivity of the second insulation layer 22”).
Regarding Claim 5, modified Yu discloses the semiconductor device according to claim 1, wherein the two or more portions of the insulating sheet (12/22) have shapes (quadrilateral shape) corresponding to arrangement of the plurality of lead frames (using the broadest reasonable interpretation of the claim language of “corresponding to arrangement”; the quadrilateral shapes of the portions of the insulating sheet 12 and 22 corresponds to and overlaps with the arrangement of the lead frames 11 and 21; as shown in Fig. 1 and Fig. 3).
Regarding Claim 6, modified Yu discloses the semiconductor device according to claim 2, wherein the two or more portions of the insulating sheet (12/22) have shapes (quadrilateral shape) corresponding to arrangement of the plurality of lead frames (using the broadest reasonable interpretation of the claim language of “corresponding to arrangement”; the quadrilateral shapes of the portions of the insulating sheet 12 and 22 corresponds to and overlaps with the arrangement of the lead frames 11 and 21; as shown in Fig. 1 and Fig. 3).
Regarding Claim 9, modified Yu discloses the semiconductor device according to claim 1, wherein the two or more portions of the insulating sheet (12/22) are asymmetrically arranged in plan view (as shown in Fig. 3; 1 and 2 (which comprise 12 and 22, respectively) are arranged asymmetrically in plan view).
Regarding Claim 10, modified Yu discloses the semiconductor device according to claim 2, wherein the two or more portions of the insulating sheet (12/22) are asymmetrically arranged in plan view (as shown in Fig. 3; 1 and 2 (which comprise 12 and 22, respectively) are arranged asymmetrically in plan view).
Regarding Claim 11, modified Yu teaches the semiconductor device according to claim 1, wherein the leads extend outside of opposing sides of the semiconductor device (as modified by Ichikawa Fig. 1 and Fig. 2; wherein leads 1c and 1d extend outside opposite sides).
Regarding Claim 12, modified Yu discloses the semiconductor device according to claim 1, wherein the lead frames (11/21) are spaced from each other in a first direction (Yu; Fig. 1; left/right), the first direction being perpendicular to a second direction that is normal to opposing sides of the semiconductor device (as shown in Fig. 3 of Yu).
Regarding Claim 13, modified Yu teaches the semiconductor device according to claim 11, wherein the lead frames (as modified by Ichikawa; 1a and 1b) are spaced from each other in a first direction (Ichikawa; X), the first direction being perpendicular to a second direction (Ichikawa; Y) that is normal to the opposing sides of the molding resin (8) (as shown in Ichikawa Fig. 1 and Fig. 2).
Regarding Claim 14, modified Yu teaches the semiconductor device according to claim 1, wherein the lead frames (as modified by Ichikawa; 1a+1c, 1b+1d) each comprise a one-piece structure (1c and 1d, respectively) that comprises a mount (where wires 4 are respectively mounted) and the leads (1c and 1d where wires are not mounted).
Regarding Claim 15, modified Yu teaches the semiconductor device according to claim 1, wherein the lead frames (as modified by Ichikawa; 1a+1c, 1b+1d) each comprise a mount (where wires 4 are respectively mounted) directly connected to the leads (1c and 1d, respectively, as shown in Ichikawa Fig. 1 and Fig. 2).
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Ichikawa and Vikas Gupta et al. (US 20240112978 A1; hereinafter Gupta).
Regarding Claim 3, modified Yu discloses the semiconductor device according to claim 1, wherein two or more semiconductor elements (4) are arranged on one portion of the insulating sheet (22) (and discloses in ¶0079 that the semiconductor element 4 may be alternatively connected to or not connected to a corresponding “line layer” which is the lead frame).
However, Yu is silent regarding wherein two or more lead frames (21) are in intimate contact with the one portion of the insulating sheet (22).
In the same field of endeavor, Gupta teaches a similar semiconductor device in Fig. 1; comprising a plurality of electronic components (30; equivalent to semiconductor elements; ¶0025) disposed on a plurality of lead frames (Fig. 1; 21, 21A, 21A; which electrically connect to 30; ¶0029), an insulating sheet with two portions (10’ and 10; ¶0025), and a heat sink with two portions (22 left and 22 right divided by G1; which dissipates heat from element 30 in a direction D1; as described in ¶0029); wherein the two portions are asymmetrically arranged (as shown in Fig. 1; wherein the left portion includes one element 30 and the right portion includes two elements 30 and is asymmetrically shaped accordingly), wherein two or more lead frames (21A, 21A; on the right side of G1) of the two or more electronic elements (30, 30; on the right side of G1) are in intimate contact with one portion of the insulating sheet (the one portion 10; on the right side of G1).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the two or more lead frames supporting the two or more electronic elements in intimate contact with the one asymmetrically larger portion of the insulating sheet (of Gupta) in the device of Yu in order to electrically connect both similar electronic elements while providing appropriate heat dissipation paths (Gupta; ¶0029-¶0030) for the respective asymmetric portions (wherein both Yu and Gupta teach asymmetrical arrangements for the plurality of semiconductor elements in respective Fig. 1) while assigning the optimal thermal conductivity to respective circuits to manage device cost (Yu; ¶0079).
Regarding Claim 4, modified Yu discloses the semiconductor device according to claim 2, wherein two or more semiconductor elements (4) are arranged on one portion of the insulating sheet (22) (and discloses in ¶0079 that the semiconductor element 4 may be alternatively connected to or not connected to a corresponding “line layer” which is the lead frame).
However, Yu is silent regarding wherein two or more lead frames (21) are in intimate contact with the one portion of the insulating sheet (22).
In the same field of endeavor, Gupta teaches a similar semiconductor device in Fig. 1; comprising a plurality of electronic components (30; equivalent to semiconductor elements; ¶0025) disposed on a plurality of lead frames (Fig. 1; 21, 21A, 21A; which electrically connect to 30; ¶0029), an insulating sheet with two portions (10’ and 10; ¶0025), and a heat sink with two portions (22 left and 22 right divided by G1; which dissipates heat from element 30 in a direction D1; as described in ¶0029); wherein the two portions are asymmetrically arranged (as shown in Fig. 1; wherein the left portion includes one element 30 and the right portion includes two elements 30 and is asymmetrically shaped accordingly), wherein two or more lead frames (21A, 21A; on the right side of G1) of the two or more electronic elements (30, 30; on the right side of G1) are in intimate contact with one portion of the insulating sheet (the one portion 10; on the right side of G1).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the two or more lead frames supporting the two or more electronic elements in intimate contact with the one asymmetrically larger portion of the insulating sheet (of Gupta) in the device of Yu in order to electrically connect both similar electronic elements while providing appropriate heat dissipation paths (Gupta; ¶0029-¶0030) for the respective asymmetric portions (wherein both Yu and Gupta teach asymmetrical arrangements for the plurality of semiconductor elements in respective Fig. 1) while assigning the optimal thermal conductivity to respective circuits to manage device cost (Yu; ¶0079).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN PRIDEMORE whose telephone number is (703)756-4640. The examiner can normally be reached Monday - Friday 8:00am - 4:00pm EST.
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NATHAN PRIDEMORE
Examiner
Art Unit 2898
/NATHAN PRIDEMORE/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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