Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Group I (claims 1-16) in the reply filed on 3/17/26 is acknowledged. Claims [17-22] are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. (see MPEP § 606.01).
This may result in slightly longer titles, but the loss in brevity of title will be more than offset by the gain in its informative value in indexing, classifying, searching, etc.
The following title is suggested:
“Semiconductor memory device having directionally reconfigured conductive patterns in word line contact region and method of manufacturing the semiconductor memory device”
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-16 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Regarding claims 1 and 2, the limitation recited in each claim, "direction between the vertical direction and the horizontal direction" is considered indefinite because it fails to particularly point out and distinctly claim the subject matter. Specifically, the phrase encompasses an undefined and potentially infinite range of angular orientations. And the claims do not provide any objective boundary, angular range, or reference frame for determining the scope. Furthermore, one of ordinary skill in the art would not be able to determine which orientations fall within the claimed scope. Accordingly, the metes and bounds of the claims are not reasonably certain.
The examiner recommends amending the limitation to: “extend in a non-horizontal and non-vertical direction”.
Regarding claims 2-10, because of their dependency on claim 1, these claims are also rejected for the reasons set forth above with respect to claim 1.
Regarding claims 11 and 16, the limitation recited in each claim, "direction between the vertical direction and the horizontal direction" is considered indefinite because it fails to particularly point out and distinctly claim the subject matter. Specifically, the phrase encompasses an undefined and potentially infinite range of angular orientations. And the claims do not provide any objective boundary, angular range, or reference frame for determining the scope. Furthermore, one of ordinary skill in the art would not be able to determine which orientations fall within the claimed scope. Accordingly, the metes and bounds of the claims are not reasonably certain.
The examiner recommends amending the limitation to: “extend in a non-horizontal and non-vertical direction”.
Regarding claims 12-16, because of their dependency on claim 11, these claims are also rejected for the reasons set forth above with respect to claim 11.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6 and 10-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Son (US 20120322252).
Regarding claim 1. Fig 2A of Son discloses A semiconductor memory device, comprising:
a gate stacked body ([0074]: GSL and 111-115) in which a plurality of interlayer insulating layers 111-115 [0074] and a plurality of conductive patterns ([0070]: GSL) are alternately stacked; and
a plurality of channel structures ([0066]/[0088]: 132/AP) disposed to extend in a vertical direction in the gate stacked body, the channel structures disposed in a cell region ([0070]: CAR),
wherein, in the cell region, the plurality of conductive patterns extend in a horizontal direction (Fig 2A), and
wherein, in a word line contact region ([0070]: CR1/CR2) adjacent to the cell region, the plurality of conductive patterns extend in the vertical direction (Fig 2A) or in a direction between the vertical direction and the horizontal direction.
Regarding claim 2. Son discloses The semiconductor memory device according to claim 1, wherein respective ends of the plurality of conductive patterns extending in the vertical direction (Fig 2A) or in the direction between the vertical direction and the horizontal direction are exposed to an external surface of the gate stacked body (Fig 2A).
Regarding claim 3. Son discloses The semiconductor memory device according to claim 2, further comprising:
a plurality of contacts ([0082]: CP) coupled to the plurality of conductive patterns (Fig 2A), respectively,
wherein each of the plurality of contacts is disposed on the gate stacked body in the word line contact region (Fig 2A).
Regarding claim 4. Son discloses The semiconductor memory device according to claim 3, wherein the plurality of contacts are coupled to respective ends of the plurality of conductive patterns exposed to the external surface of the gate stacked body (Fig 2A).
Regarding claim 5. Son discloses The semiconductor memory device according to claim 1, further comprising:
an insulating layer 124 [0081] configured to separate the gate stacked body in the word line contact region (Fig 2A).
Regarding claim 6. Son discloses The semiconductor memory device according to claim 5, wherein the insulating layer extends in the vertical direction (Fig 2A).
Regarding claim 10. Son discloses The semiconductor memory device according to claim 1, wherein the plurality of conductive patterns extending in the horizontal direction in the cell region (Fig 2A) and the plurality of conductive patterns extending in the vertical direction (Fig 2A) or in the direction between the vertical direction and the horizontal direction in the word line contact region are made of substantially an identical material (Fig 2A).
Regarding claim 11. Fig 2A of Son discloses A semiconductor memory device, comprising:
a gate stacked body ([0074]: GSL and 111-115) formed in a cell region ([0070]: CAR) and in a word line contact region ([0070]: CR1/CR2) adjacent to the cell region in a horizontal direction (Fig 2A); and
a plurality of channel structures ([0066]/[0088]: 132/AP) disposed to extend in a vertical direction in the gate stacked body, the channel structures disposed in the cell region,
wherein the gate stacked body includes a plurality of interlayer insulating layers 111-115 [0074] and a plurality of conductive patterns ([0070]: GSL) that are alternately stacked, and
wherein, in the cell region, the plurality of conductive patterns extend in the horizontal direction (Fig 2A), and
wherein, in the word line contact region, the plurality of conductive patterns extend in the vertical direction (Fig 2A) or in a direction between the vertical direction and the horizontal direction and are then exposed to an upper surface of the gate stacked body (Fig 2A).
Regarding claim 12. Son discloses The semiconductor memory device according to claim 11, further comprising:
a plurality of contacts ([0082]: CP) disposed on the gate stacked body in the word line contact region and respectively coupled to the plurality of conductive patterns exposed to the upper surface of the gate stacked body (Fig 2A).
Regarding claim 13. Son discloses The semiconductor memory device according to claim 12, wherein the plurality of contacts are disposed at a position equal to or higher than a position of the upper surface of the gate stacked body (Fig 2A).
Regarding claim 14. Son discloses The semiconductor memory device according to claim 11, further comprising:
an insulating layer 124 [0081] configured to separate the gate stacked body in the word line contact region (Fig 2A).
Regarding claim 15. Son discloses The semiconductor memory device according to claim 14, wherein the insulating layer extends in the vertical direction (Fig 2A).
Regarding claim 16. Son discloses The semiconductor memory device according to claim 11, further comprising:
a buffer layer 116 formed on the gate stacked body in the cell region,
wherein each of the plurality of conductive patterns extending in the vertical direction (Fig 2A) or the direction between the vertical direction and the horizontal direction in the word line contact region extends to a position equal to (Fig 2A) or higher than an upper surface of the buffer layer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over by Son (US 20120322252) in view of Lee (US 20210036002).
Regarding claim 7. Son discloses The semiconductor memory device according to claim 1. But Son does not explicitly disclose the claimed specific location of further comprising:
a source line layer disposed on the gate stacked body and coupled to respective upper portions of the plurality of channel structures; and
a bit line connection structure disposed under the gate stacked body and coupled to respective lower portions of the plurality of channel structures.
However, Fig 2 of Lee discloses a source line layer ([0037]: CSL) disposed on the gate stacked body ([0037]: GST) and coupled to respective upper portions of the plurality of channel structures ([0037]: CH); and
a bit line connection structure 41A [0038] disposed under the gate stacked body and coupled to respective lower portions of the plurality of channel structures (Fig 2).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Son’s device to have the Lee’s structure for the purpose of providing enhanced GSL turn-off characteristic and lower overall source resistance, which enhancing the overall performance and reliability of the 3D NAND memory device, especially during high-speed operations.
Regarding claim 8. Son in view of Lee discloses The semiconductor memory device according to claim 7, Lee discloses further comprising:
a first coupling structure (C1) coupled to the bit line connection structure, and including a first bonding metal 71 [0066], a surface of which is exposed to outside of the first coupling structure;
a second coupling structure (C2) including a second bonding metal 93 [0066] contacting the first bonding metal of the first coupling structure (Fig 2); and
a complementary metal-oxide semiconductor (CMOS) circuit structure ([0055]: TR) coupled to the second coupling structure and including a plurality of transistors (Fig 2).
Regarding claim 9. Son in view of Lee discloses The semiconductor memory device according to claim 7, Lee discloses further comprising:
a buffer layer (Fig 4: ILD) disposed between an upper portion of the gate stacked body in the cell region and the source line layer (Fig 4),
wherein the plurality of channel structures are coupled to the source line layer by penetrating the buffer layer (Fig 4).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Changhyun Yi whose telephone number is (571)270-7799. The examiner can normally be reached Monday-Friday: 8A-4P.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Changhyun Yi/Primary Examiner, Art Unit 2812
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