Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Amendment filed on 8/11/26 has been entered.
Response to Arguments
Applicant’s arguments have been fully considered but they are moot because the arguments do not apply to any of the references being used in the current rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-16 are rejected under 35 U.S.C. § 103 as being unpatentable over Son et al. (US 20120322252; “Son”) in view of Tsutsumi et al. (US 20220157842; “Tsutsumi”).
Regarding claim 1, Son discloses a semiconductor memory device comprising:
a gate stacked body in which a plurality of interlayer insulating layers (111–115) and a plurality of conductive patterns (GSL, WL1–WL4, and SSL) are alternately stacked (Fig. 2A; paragraphs [0070] and [0074]); and
a plurality of channel structures (active memory string structures AP, with surrounding information storage layers 132) disposed to extend in a vertical direction in the gate stacked body, the channel structures disposed in a cell region (CAR; Fig. 2A; paragraphs [0066], [0070], [0086], and [0088]);
wherein, in the cell region, the plurality of conductive patterns extend in a horizontal direction (bottom portions BP of GSL, WL1–WL4, and SSL extending horizontally through CAR; Fig. 2A; paragraph [0076]); and
wherein, in a word line contact region adjacent to the cell region, the plurality of conductive patterns extend in the vertical direction or in an inclined direction (contact portions CT extending upward in contact regions CR1/CR2 adjacent to CAR; Fig. 2A; paragraphs [0070] and [0077]–[0078]).
But Son does not expressly disclose that one of the plurality of channel structures contacts a first source line layer, and another of the plurality of channel structures contacts a second source line layer, wherein the first source line layer is spaced apart from the second source line layer.
However, Tsutsumi teaches that one of the plurality of channel structures contacts a first source line layer (one channel 60 within a memory opening fill structure 58 contacts one source layer 109; Figs. 25B and 26B; paragraphs [0195] and [0220]), and another of the plurality of channel structures contacts a second source line layer (another channel 60 contacts a different source layer 109; Fig. 26B; paragraphs [0198] and [0220]), wherein the first source line layer is spaced apart from the second source line layer (neighboring source layers 109 separated by trenches 21 containing dielectric isolation structures 23; Fig. 26B; paragraphs [0196], [0198], and [0223]).
Son already provides a common source region in substrate 101, which may have a plate configuration, and connects the source ends of its vertical memory strings to that region (paragraphs [0068] and [0086]). Tsutsumi further teaches patterning a substrate semiconductor layer into separated source layers (Fig. 20A; paragraph [0184]).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Son’s common-source arrangement to provide spaced-apart source-line layers contacting respective groups of channel structures, as taught by Tsutsumi, for the purpose of enabling smaller erase units and reducing operational leakage current, as explained in Tsutsumi’s paragraph [0197] with reference to Fig. 27.
There would have been a reasonable expectation of success because the proposed modification applies the disclosed source-partitioning technique to the common-source connection already present in Son. Each resulting source-line layer would continue to provide a source connection for its associated channel structures. The modification would partition the source connections in the cell region while retaining Son’s alternating gate stack, horizontal conductive portions, and upwardly extending contact portions. The resulting device would therefore include one channel structure contacting a first source-line layer and another channel structure contacting a second source-line layer spaced apart from the first, as claimed.
Regarding claim 2. Son in view Tsutsumi discloses The semiconductor memory device according to claim 1, Son discloses wherein respective ends of the plurality of conductive patterns extending in the vertical direction (Fig 2A) or in the direction between the vertical direction and the horizontal direction are exposed to an external surface of the gate stacked body (Fig 2A).
Regarding claim 3. Son in view Tsutsumi discloses The semiconductor memory device according to claim 2, Son discloses further comprising:
a plurality of contacts ([0082]: CP) coupled to the plurality of conductive patterns (Fig 2A), respectively,
wherein each of the plurality of contacts is disposed on the gate stacked body in the word line contact region (Fig 2A).
Regarding claim 4. Son in view Tsutsumi discloses The semiconductor memory device according to claim 3, Son discloses wherein the plurality of contacts are coupled to respective ends of the plurality of conductive patterns exposed to the external surface of the gate stacked body (Fig 2A).
Regarding claim 5. Son in view Tsutsumi discloses The semiconductor memory device according to claim 1, Son discloses further comprising
an insulating layer 124 [0081] configured to separate the gate stacked body in the word line contact region (Fig 2A).
Regarding claim 6. Son in view Tsutsumi discloses The semiconductor memory device according to claim 5, Son discloses wherein the insulating layer extends in the vertical direction (Fig 2A).
Regarding claim 7, Son in view of Tsutsumi teaches the semiconductor memory device according to claim 1, Son does not expressly disclose the claimed positioning of the source line layer above the gate stacked body and the bit line connection structure below the gate stacked body.
However, Fig. 26B of Tsutsumi discloses:
a source line layer (patterned source-level layer 109) disposed on the gate stacked body (alternating insulating layers 132/232 and conductive layers 146/246) and coupled to respective upper portions of the plurality of channel structures (60 within memory opening fill structures 58; paragraphs [0195]–[0196] and [0220]); and
a bit line connection structure (bit lines 98 and associated contact structures 88/188) disposed under the gate stacked body and coupled to respective lower portions of the plurality of channel structures (through drain regions 63; Fig. 26B; paragraphs [0170], [0181], and [0226]).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Son’s device, incorporating the separated source-line arrangement discussed for claim 1, to have the source line layer above the gate stacked body and the bit line connection structure below the gate stacked body, as taught by Tsutsumi. This arrangement would place the bit-line routing toward the bonding interface and provide access to the opposite source-side surface for forming and patterning the separated source-line layers following bonding (Tsutsumi, paragraphs [0178]–[0181] and [0191]–[0196]).
There would have been a reasonable expectation of success because Tsutsumi demonstrates that terminal arrangement in a vertical-channel memory device. The proposed modification would apply that arrangement to Son’s cell region, with the source and drain selection functions positioned at the corresponding channel ends. Son’s upwardly extending word-line contact portions would provide the contact-region geometry discussed for claim 1.
Regarding claim 8, Son in view of Tsutsumi teaches the semiconductor memory device according to claim 7. Tsutsumi further discloses:
a first coupling structure coupled to the bit line connection structure, and including a first bonding metal, a surface of which is exposed to outside of the first coupling structure (the memory-side interconnect and bonding structure, including bonding pads 998 having bonding faces at the memory-side bonding surface; Figs. 18A and 26B; paragraphs [0170] and [0177]–[0179]);
a second coupling structure including a second bonding metal contacting the first bonding metal of the first coupling structure (the logic-side interconnect and bonding structure, including bonding pads 798 contacting pads 998 through metal-to-metal bonding; Figs. 17A, 18A, and 26B; paragraphs [0175]–[0179]); and
a complementary metal-oxide semiconductor (CMOS) circuit structure coupled to the second coupling structure and including a plurality of transistors (peripheral circuit 710, connected through interconnect structures 780 to pads 798; Fig. 17A; paragraphs [0173]–[0176]).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Tsutsumi’s corresponding interconnect and metal-bonding structures into the device of claim 7 to electrically couple the memory array to its CMOS operating circuitry. The mating bonding metals would provide the electrical interface between the separately formed memory and logic structures, with a reasonable expectation of success based on Tsutsumi’s disclosed bonded assembly.
Regarding claim 9, Son in view of Tsutsumi teaches the semiconductor memory device according to claim 7. Tsutsumi further discloses:
a buffer layer disposed between an upper portion of the gate stacked body in the cell region and the source line layer (the terminal source-side insulating layer 132 between source layer 109 and the underlying alternating gate stack; Figs. 25B and 26B; paragraphs [0083]–[0084] and [0195]),
wherein the plurality of channel structures are coupled to the source line layer by penetrating the buffer layer (channels 60 extend through that terminal insulating layer 132 and contact source layer 109; Figs. 25B and 26B; paragraph [0195]). The terminal source-side layer 132 is mapped to the claimed buffer layer, and the underlying alternating conductive and insulating layers are mapped to the gate stacked body.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include this source-side insulating layer when implementing Tsutsumi’s upper-source arrangement in the device of claim 7, thereby electrically separating the source line layer from the adjacent gate conductor while permitting the channel structures to extend through the insulating layer to the source line layer.
Regarding claim 10. Son in view Tsutsumi discloses The semiconductor memory device according to claim 1, Son discloses wherein the plurality of conductive patterns extending in the horizontal direction in the cell region (Fig 2A) and the plurality of conductive patterns extending in the vertical direction (Fig 2A) or in the direction between the vertical direction and the horizontal direction in the word line contact region are made of substantially an identical material (Fig 2A).
Regarding claim 11, Son discloses a semiconductor memory device comprising:
a gate stacked body formed in a cell region (CAR) and in a word line contact region (CR1/CR2) adjacent to the cell region in a horizontal direction (Fig. 2A; paragraphs [0070] and [0074]); and
a plurality of channel structures (active memory string structures AP, with surrounding information storage layers 132) disposed to extend in a vertical direction in the gate stacked body, the channel structures disposed in the cell region (CAR; Fig. 2A; paragraphs [0066], [0070], [0086], and [0088]);
wherein the gate stacked body includes a plurality of interlayer insulating layers (111–115) and a plurality of conductive patterns (GSL, WL1–WL4, and SSL) that are alternately stacked (Fig. 2A; paragraph [0074]);
wherein, in the cell region, the plurality of conductive patterns extend in the horizontal direction (bottom portions BP extending horizontally through CAR; Fig. 2A; paragraph [0076]); and
wherein, in the word line contact region, the plurality of conductive patterns extend in the vertical direction or in an inclined direction and are exposed to an upper surface of the gate stacked body (contact portions CT extending upward in CR1/CR2 and terminating at the upper surface of the stack for connection to contact plugs; Fig. 2A; paragraphs [0077]–[0078] and [0082]–[0084]).
But Son does not expressly disclose that one of the plurality of channel structures contacts a first source line layer, and another of the plurality of channel structures contacts a second source line layer, wherein the first source line layer is spaced apart from the second source line layer.
However, Tsutsumi teaches this arrangement through different channels 60 contacting respective source layers 109, with neighboring layers separated by dielectric isolation structures 23 (Figs. 25B and 26B; paragraphs [0195]–[0198] and [0220]–[0223]).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Son’s common-source arrangement to provide spaced-apart source-line layers contacting respective groups of channel structures, as taught by Tsutsumi, for the purpose of enabling smaller erase units and reducing operational leakage current (Tsutsumi, Fig. 27; paragraph [0197]).
There would have been a reasonable expectation of success because Tsutsumi demonstrates that terminal arrangement in a vertical-channel memory device. The source connections would be partitioned while Son’s gate stacked body would continue to extend through the cell and word line contact regions, with the conductive patterns extending upward to the upper surface of the stack in the contact region. Accordingly, the proposed modification would provide the claimed separated source-line layers and respective channel contacts together with the remaining structure disclosed by Son.
Regarding claim 12. Son in view Tsutsumi discloses The semiconductor memory device according to claim 11, Son discloses further comprising
a plurality of contacts ([0082]: CP) disposed on the gate stacked body in the word line contact region and respectively coupled to the plurality of conductive patterns exposed to the upper surface of the gate stacked body (Fig 2A).
Regarding claim 13. Son in view Tsutsumi discloses The semiconductor memory device according to claim 12, Son discloses wherein the plurality of contacts are disposed at a position equal to or higher than a position of the upper surface of the gate stacked body (Fig 2A).
Regarding claim 14. Son in view Tsutsumi discloses The semiconductor memory device according to claim 11, Son discloses further comprising
an insulating layer 124 [0081] configured to separate the gate stacked body in the word line contact region (Fig 2A).
Regarding claim 15. Son in view Tsutsumi discloses The semiconductor memory device according to claim 14, Son discloses wherein the insulating layer extends in the vertical direction (Fig 2A).
Regarding claim 16. Son in view Tsutsumi discloses The semiconductor memory device according to claim 11, Son discloses further comprising:
a buffer layer 116 formed on the gate stacked body in the cell region;
wherein each of the plurality of conductive patterns extending in the vertical direction (Fig 2A) or the inclined direction in the word line contact region extends to a position equal to (Fig 2A) or higher than an upper surface of the buffer layer.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Changhyun Yi whose telephone number is (571)270-7799. The examiner can normally be reached Monday-Friday: 10A-3P.
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/Changhyun Yi/Primary Examiner, Art Unit 2812
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