DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 1 in the reply filed on Jun. 8th 2026 is acknowledged. Claims 1-3, 8-11 and 13-20 are examined in this office action. Claims 4-7 and 12 are withdrawn from further consideration.
Claim Objections
Claim 16 is objected to because of the following informalities:
In claim 16, line 5, “the top surface" should read “a top surface.”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-3 and 8-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Where applicant acts as his or her own lexicographer to specifically define a term of a claim contrary to its ordinary meaning, the written description must clearly redefine the claim term and set forth the uncommon definition so as to put one reasonably skilled in the art on notice that the applicant intended to so redefine that claim term. Process Control Corp. v. HydReclaim Corp., 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999). The term “operable” in "when the chip is operated in the stacking mode..." in line 14 and "when the chip is operated in the side-by-side mode" in line 18 of claim 1 is used by the claim to mean “configured,” while the accepted meaning is “setting ready for use.” The term is indefinite because the specification does not clearly redefine the term. The chip switch from the stacking mode to the side-by-side mode is not in the same setting and ready to use. The switch mode need be configured to move elements and different wiring. In addition, these limitations of “when” are If-then statements, which are indefinite. The limitations do not have to be true, in which case the rest of the limitation is irrelevant. Therefore, the limitations of “when” do not carry patentable weight, since it is unclear if the required conditions are met. For examination purposes, examiner has interpreted "when the chip is operated in the stacking mode..." and "when the chip is operated in the side-by-side mode" to be read as "the chip is configured in the stacking mode… Or… configured in the side-by-side mode". Claims 2-3 and 8-11 would also be rejected under 35 U.S.C. 112(b) because they are dependent on claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3 and 8-11 are rejected under 35 U.S.C. 103 as being unpatentable over Chung et al. (US 20210104480) in view of Sirocka et al. (US 20170207195) and Lo et al. (US 20210118846).
Regarding claim 1, Chung teaches an integrated circuit structure (Abstract), comprising:
a substrate (fig. 6, package substrate 2; para. 0039) having an upper surface (supporting surface 2a; para. 0039) and a lower surface (a bottom surface 2b; para. 003) opposite to the first surface (2a); and
a chip (chip 1; para. 0035) comprising a first pad set (flip-chip power pads P1, flip-chip ground pads G1; para. 0033), a signal pad set (signal pads S; para. 0029), and a second pad set (wire-bonding power pads P2, wire-bonding ground pads G2; para. 0033), wherein the first pad set (P1, G1), the signal pad set (S), and the second pad set (P2, G2) are sequentially arranged on a top surface of the chip (from left to right on top surface of 1) along a layout direction (horizontal direction), and the chip (1) is selectively operable (selectively connect chips or wires to the pads) in a stacking mode (flip-chip mode) through the first pad set (P1, G1) or a side-by-side mode (wire-bonding mode) through the second pad set (P2, G2);
wherein, when the chip is operated in the stacking mode, the chip is stacked onto the electronic component, the signal pad set is electrically coupled to the electronic component in a wire-bonding manner, and the first pad set is electrically coupled to the substrate in a wire-bonding manner;
wherein, when the chip is operated in the side-by-side mode (wire-bonding mode), the chip (1) is disposed on the upper surface of the substrate (2a of 2), and the second pad set (p2, G2) is electrically coupled to the substrate (2) in a wire-bonding manner (wire).
Chung fails to explicitly teach a connection circuit, wherein the first pad set and the second pad set are electrically coupled to each other through the connection circuit, so that the chip is selectively operable in the first pad set or the second pad set.
However, Sirocka teaches a connection circuit (Sirocka: fig. 2, integrated circuit 250; para. 0018), wherein the first pad set (Sirocka: second pad state with duplicate die pads 226; para. 0019, similar to pads with P1, G1 of Chung) and the second pad set (Sirocka: first pad state with second die pads 225; para. 0019, similar to pads with P2, G2 of Chung) are electrically coupled to each other through the connection circuit (Sirocka: 250), so that the chip (Sirocka: memory die 210; para. 0016, similar to 1 of Chuang) is selectively operable (selectively first or second pad state to enable pads) in the first pad set (Sirocka: first pad state) or the second pad set (Sirocka: second pad state).
Sirocka and Chung are considered to be analogous to the claimed invention because they are in the same field of die package devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a connection circuit as taught by Sirocka.
Doing so would realize flexible pad states to minimizing the length of the bond wires and improve electrical performance (Sirocka: para. 0022).
In addition, Chung in view of Sirocka fails to explicitly teach an electronic component disposed on the upper surface, wherein the electronic component is electrically coupled to the substrate in a wire-bonding manner;
the signal pad set is electrically coupled to the electronic component.
However, Lo teaches an electronic component (Lo: fig. 1, die C2; para. 0002) disposed on the upper surface (Lo: top surface of package substrate S; para. 0002, similar to 2 of Chung), wherein the electronic component (Lo: C2) is electrically coupled to the substrate (Lo: S) in a wire-bonding manner (Lo: bonding wire W2; para. 0002);
the signal pad set (Lo: pad on die C1 have signal connection through W1 and S; para. 0002, similar to S of Chung) is electrically coupled to the electronic component (Lo: C2).
Lo, Sirocka and Chung are considered to be analogous to the claimed invention because they are in the same field of die package devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add an electronic component as taught by Lo.
Doing so would realize a structure to increase the capacity of the semiconductor package (Lo: para. 0002).
Regarding claim 2, Chung in view of Sirocka and Lo further teaches the integrated circuit structure according to claim 1, wherein the first pad set (Chung: fig. 6, P1, G1) comprises a plurality of first pads (Chung: P1, G1), the signal pad set (Chung: S) comprises a plurality of signal pads (Chung: S), and the second pad set (Chung: P2, G2) comprises a plurality of second pads (Chung: P2, G2) respectively corresponding in position (opposite side) to the first pads (Chung: P1, G1), and wherein each of the first pads (Chung: P1, G1) and the corresponding second pad (Chung: P2, G2) are electrically coupled to each other through the connection circuit (Sirocka: 250) so as to be operable by choosing one (Sirocka: enable 225 or 226) therefrom.
Regarding claim 3, Chung in view of Sirocka and Lo further teaches the chip according to claim 2, wherein any one of the first pads and the corresponding second pad (Chung: fig. 6, P1. G1 and P2, G2) are jointly configured to transmit electricity (Chung: P1, P2 with power) or are jointly configured to be grounded (Chung: G1, G2 are grounded).
Regarding claim 8, Chung in view of Sirocka and Lo further teaches the chip according to claim 2, wherein the first pads of the first pad set (Chung: fig. 1, 2, P1. G1) are in an annular arrangement (Chung: around the center), the signal pads of the signal pad set (Chung: S) are in an annular arrangement (Chung: around in the middle), and the second pads of the second pad set (Chung: P2, G2) are in an annular arrangement (Chung: around the edge), and wherein the first pad set (Chung: P1, G1), the signal pad set (Chung: S), and the second pad set (Chung: P2, G2) are sequentially arranged from an interior of the top surface toward an exterior of the top surface (Chung: from center to the edge of the top surface of 1).
Regarding claim 9, Chung in view of Sirocka and Lo further teaches the chip according to claim 8, wherein the top surface of the chip (Chung: fig. 6, top surface of 1) has a plurality of outer edges (Chung: fig. 1, 4 sides outer edges), wherein at least one of the first pads (Chung: P1, G1), at least one of the signal pads (Chung: S), and at least one of the second pads (Chung: P2, G2) are arranged adjacent to one of the outer edges (one side) and are jointly defined as an operation unit (Sirocka: unit enable in first pad state), and wherein the chip (Chung: fig. 6,1) is electrically coupled to the electronic component (Lo: C2) through the signal pads (Chung: S) of the operation unit (Sirocka: unit in first pad state).
Regarding claim 10, Chung in view of Sirocka and Lo further teaches the integrated circuit structure according to claim 2, wherein the top surface of the chip (Chung: fig. 6, top surface of 1) includes at least one third pad (Chung: in an alternative consideration, one S as third pad instead of signal pad) arranged between the first pad set (Chung: P1, G1) and the second pad set (Chung: P2, G2), and wherein the at least one third pad (one S) is electrically coupled to at least one of the first pads (Chung: P1, G1) and the corresponding second pad (Chung: P2, G2).
Regarding claim 11, Chung in view of Sirocka and Lo further teaches the integrated circuit structure according to claim 1, wherein, when the chip (Lo: fig. 1, C1) is operated in the side-by-side mode, the signal pad set of the chip (Lo: pad on die C1 have signal connection) is electrically coupled to the substrate (Lo: S) in a wire-bonding manner (Lo: W2), and the chip (Lo: C1) and the electronic component (Lo: C2) are electrically coupled to each other through the substrate (Lo: S).
Claims 13-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chung in view of Sirocka.
Regarding claim 13, Chung teaches a chip (fig. 6, chip 1; para. 0035), comprising:
a first pad set (wire-bonding power pads P2, wire-bonding ground pads G2; para. 0033) including a plurality of first pads (P2, G2);
a second pad set (flip-chip power pads P1, flip-chip ground pads G1; para. 0024) including a plurality of second pads (P1, G1) respectively corresponding in position (same line) to the first pads (P2, G2); and
a signal pad set (signal pads S; para. 0029) arranged between the first pad set (P2, G2) and the second pad set (P1, G1) and including a plurality of signal pads (S).
Chung fails to explicitly teach a connection circuit, wherein each of the first pads and the corresponding second pad are electrically coupled to each other through the connection circuit so as to be operable by choosing one therefrom.
However, Sirocka teaches a connection circuit (Sirocka: fig. 2, integrated circuit 250; para. 0018), wherein each of the first pads (Sirocka: first pad state with second die pads 225; para. 0019, similar to pads with P2, G2 of Chung) and the corresponding second pad (Sirocka: second pad state with duplicate die pads 226; para. 0019, similar to pads with P1, G1 of Chung) are electrically coupled to each other through the connection circuit (Sirocka: 250) so as to be operable by choosing one (Sirocka: enable 225 or 226) therefrom.
Sirocka and Chung are considered to be analogous to the claimed invention because they are in the same field of die package devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a connection circuit as taught by Sirocka.
Doing so would realize flexible pad states to minimizing the length of the bond wires and improve electrical performance (Sirocka: para. 0022).
Regarding claim 14, Chung in view of Sirocka further teaches the chip according to claim 13, wherein any one of the first pads and the corresponding second pad (Chung: fig. 6, P2. G2 and P1, G1) are jointly configured to transmit electricity (Chung: P1, P2 with power) or are jointly configured to be grounded (Chung: G1, G2 are grounded).
Regarding claim 15, Chung in view of Sirocka further teaches the chip according toclaim 13, wherein, in any one of the first pads and the corresponding second pad (Chung: fig. 6, P2. G2 and P1, G1), one is configured to be connected to a wire (Chung: P2, G2 with wire), and another one is configured to be unconnected to any wire (Chung: P1, G1 without wire).
Regarding claim 16, Chung in view of Sirocka further teaches the chip according to claim 13, wherein the first pads of the first pad set (Chung: fig. 1, 2, P2. G2) are in an annular arrangement (Chung: around the edge), the signal pads of the signal pad set (Chung: S) are in an annular arrangement (Chung: around in the middle), and the second pads of the second pad set (Chung: P1, G1) are in an annular arrangement (Chung: around in the center), and wherein the first pad set (Chung: P2, G2), the signal pad set (Chung: S), and the second pad set (Chung: P1, G1) are sequentially arranged from an interior of the top surface toward an exterior of the top surface (Chung: from center to the edge of the top surface of 1).
Regarding claim 17, Chung in view of Sirocka further teaches the chip according to claim 13, wherein the top surface of the chip (Chung: fig. 6, top surface of 1) has a plurality of outer edges (Chung: fig. 1, 4 sides outer edges), wherein a part of the first pads (Chung: P2, G2), a part of the signal pads (Chung: S), and a part of the second pads (Chung: P1, G1) are arranged adjacent to one of the outer edges (one side) and are jointly defined as an operation unit (Sirocka: unit enable in first pad state), and wherein the chip (Chung: fig. 6,1) is configured to be electrically coupled to an electronic component (Chung: package substrate 2; para. 0039) through the signal pads (Chung: S) of the operation unit (Sirocka: unit in first pad state).
Regarding claim 18, Chung teaches a chip (fig. 6, chip 1; para. 0035), comprising:
a main portion (main portion of 1) including a top surface (first surface 1a; para. 0022);
a pad set (flip-chip power pads P1, flip-chip ground pads G1, wire-bonding power pads P2, wire-bonding ground pads G2; para. 0024, 0033) including a first pad (P1, G1) and a second pad (P2, G2) both are arranged on the top surface (1a);
a signal pad (signal pads S; para. 0029) arranged on the top surface (1a) of the main portion, wherein the first pad (P1, G1), the signal pad (S), and the second pad (P2, G2) are arranged sequentially in a predetermined order (P1, G1, S, P2, G2 order) along a layout direction (horizontal direction) defined toward a periphery of the chip (edge of 1).
Chung fails to explicitly teach a circuit assembly that is arranged under the top surface
a signal pad electrically coupled to the circuit assembly
a connection circuit arranged under the top surface, wherein the connection circuit includes a first segment electrically coupled to the first pad, a second segment electrically coupled to the second pad, and a common segment that is electrically coupled to the circuit assembly;
wherein, when the circuit assembly is electrically coupled to an object outside of the chip through the pad set, the pad set is operable by choosing one of the first pad and the second pad to be electrically coupled to the object in a wire-bonding manner.
However, Sirocka teaches a circuit assembly (Sirocka: fig. 2, integrated circuit 250; para. 0018) that is arranged under the top surface (inside under top surface);
a signal pad (Sirocka: additional die bond pads 227 with signals; para. 0017, similar to S of Chuang) electrically coupled to the circuit assembly (Sirocka: 250);
a connection circuit (Sirocka: fig. 5, conductive lines 564; para. 0026) arranged under the top surface (inside under top surface), wherein the connection circuit (Sirocka: 564) includes a first segment (Sirocka: 564 to duplicate die pads 226; para. 0019, similar to pads with P1, G1 of Chung) electrically coupled to the first pad (Sirocka: 226), a second segment (Sirocka: 564 to second die pads 225; para. 0019, similar to pads with P2, G2 of Chung) electrically coupled to the second pad (Sirocka: 225), and a common segment (Sirocka: 564 to 250) that is electrically coupled to the circuit assembly (Sirocka: 250);
wherein, when the circuit assembly (Sirocka: 250) is electrically coupled to an object (Chung: fig. 6, package substrate 2; para. 0039) outside of the chip (Chuang: 1) through the pad set (Chuang: P1, P2, S, P2, G2), the pad set (Chuang: P1, P2, S, P2, G2) is operable by choosing (Sirocka: enable first pad state with 225 or second pad state with 226; para. 0019) one of the first pad (Sirocka: 225, similar to pads with P2, G2 of Chung) and the second pad (Sirocka: 226, similar to pads with P1, G1 of Chung) to be electrically coupled to the object (Chuang: 2) in a wire-bonding manner (Chuang: wire).
Sirocka and Chung are considered to be analogous to the claimed invention because they are in the same field of die package devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a circuit assembly and a connection circuit as taught by Sirocka.
Doing so would realize flexible pad states to minimizing the length of the bond wires and improve electrical performance (Sirocka: para. 0022).
Regarding claim 20, Chung in view of Sirocka further teaches the chip according to claim 18, wherein, when the second pad (Chung: fig. 6, P2, G2) and the signal pad (Chung: S) are configured for a wire-bonding process (wires), the second pad (Chung: P2, G2) is capable of being connected to a second wire (Chung: ground bonding wires 30G′; para. 0053), and the signal pad (Chung: S) is capable of being connected to a signal wire (Chung: signal bonding wires 30S′; para. 0053) that is not shorter than the second wire (Chung: 30G′).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Chung in view of Sirocka as applied to claim 18 above, and further in view of Chen et al. (US 20190341366).
Regarding claim 19, Chung in view of Sirocka teaches the chip according to claim 18, wherein, when the signal pad (S) are configured for a wire-bonding process (signal bonding wires 30S'; para. 0053),
Chung in view of Sirocka fails to explicitly teach the first pad are configured for a wire-bonding process,
the first pad is capable of being connected to a first wire, and the signal pad is capable of being connected to a signal wire that is not longer than the first wire.
However, Chen teaches the first pad (Chen: fig. 10, signal transfer bond pads 126; para. 0036, similar to S of Chuang) are configured for a wire-bonding process (wires),
the first pad (Chen: dummy die bond pads 128; para. 0044, similar to P2 or G2 of Chuang) is capable of being connected to a first wire (Chen: dummy wire bonds 132; para. 0044), and the signal pad (Chen: 126) is capable of being connected to a signal wire (Chen: top wire bonds 130; para. 0042) that is not longer than the first wire (Chen: 132).
Chen, Sirocka and Chung are considered to be analogous to the claimed invention because they are in the same field of die package devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a signal wire that is not longer than the first wire as taught by Chen.
Doing so would realize a stack structure to be more efficiently use package footprint (Chen: para. 0004).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHIJUN XU whose telephone number is (571)270-3447. The examiner can normally be reached Monday-Thursday 9am-5pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ZHIJUN XU/Examiner, Art Unit 2818
/BRIAN TURNER/Primary Examiner, Art Unit 2818
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