DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election without traverse of Species A of Fig. 1, claims 1-10, in the reply filed on March 12, 2026 is acknowledged. Therefore, claims 1-10 are presented for examination.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-7 and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over by Jang (US 2022/0130799, Foreign priority: Oct. 27, 2020 (KR)) in view of Jeong et al. (KR 20110028746, hereinafter Jeong).
Regarding claim 1, Jang discloses for a semiconductor package, comprising:
a lower semiconductor chip (under bump metal 101/chip bump BP, Fig. 1);
a first semiconductor chip (first semiconductor chip 100, Fig. 1) stacked on the lower semiconductor chip (101/BP, Fig. 1); and
a second semiconductor chip (second semiconductor chip 200, Fig. 1) stacked on the lower semiconductor chip (101/BP, Fig. 1),
wherein the first semiconductor chip (100, Fig. 1) includes:
a first semiconductor substrate (first semiconductor body 110, Fig. 1);
a first through electrode (first through-electrode structure 120, Fig. 1) vertically penetrating the first semiconductor substrate (110, Fig. 1);
a first upper pad (upper pad structure PS on the right through-electrode 120, Fig. 2) electrically connected to the first through electrode (120, Fig. 2) on an upper surface of the first semiconductor substrate (upper surface of 110, Fig. 2);
an upper protective layer (upper insulating layer 185, Fig. 2) at least partially surrounding the first upper pad (PS, Fig. 2) on the upper surface of the first semiconductor substrate (upper surface of 110, Fig. 2);
a first circuit layer (lower internal insulating layer 130 having first internal circuit structure ICS1, Fig. 1) disposed on a lower surface of the first semiconductor substrate (lower surface of 110, Fig. 1); and
a first lower pad (chip pad 105, Fig. 1) connected to the first through electrode (120, Fig. 1) through the first circuit layer (130 having ICS1, Fig. 1) on a lower surface of the first circuit layer (lower surface of 130, Fig. 2),
wherein the second semiconductor chip (200, Fig. 1) includes:
a second semiconductor substrate (second semiconductor body 210, Fig. 1);
a second through electrode (second through-electrode 220, Fig. 1) vertically penetrating the second semiconductor substrate (210, Fig. 1);
a second upper pad (upper pad structure PS on the right through-electrode 220, Fig. 2) electrically connected to the second through electrode (220, Fig. 2) on an upper surface of the second semiconductor substrate (upper surface of 210, Fig. 2);
a second circuit layer (second lower internal insulating layer 230 having second internal circuit structure ICS2, Fig. 2) disposed on a lower surface of the second semiconductor substrate (lower surface of 210, Fig. 2);
a second lower pad (lower bonding pad PAD3, Fig. 2) electrically connected to the second through electrode (220, Fig. 2) through the second circuit layer (230, Fig. 2) on a lower surface of the second circuit layer (lower surface of 230, Fig. 2); and
a lower protective layer (lower insulating layer 215, Fig. 2) at least partially surrounding the second lower pad (PAD3, Fig. 2) on the lower surface of the second circuit layer (lower surface of 230, Fig. 2),
wherein the lower protective layer (215, Fig. 2) is in direct contact with the upper protective layer (185, Fig. 2),
wherein the second lower pad (PAD3, Fig. 2) is in contact with the first upper pad (PS, Fig. 2) and forms an integral body therewith (PS/PAD3, Fig. 2).
Jang does not explicitly disclose that the first through electrode is horizontally spaced apart from the second through electrode, in a plan view.
However, Jeong discloses for a stacked semiconductor package that the package includes a plurality of semiconductor chips are vertically stacked (Fig. 1b) and each semiconductor chip includes the plurality of through silicon vias (TSV) 18 (Fig. 1b); Jeong further discloses that the TSVs 18 in the lower semiconductor chip are horizontally spaced apart from the TSVs 18 in an upper semiconductor chip in a plan view (Fig. 1b), therefore, Jeong teaches an arrangement of through electrodes or vias in stacked semiconductor chips is laterally offset rather than vertically aligned.
Since both Jang and Jeong teach a semiconductor package structure, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the vertically aligned through-electrodes of Jang to be horizontally offset in a plan view, as disclosed by Jeong, in order to reduce electrical noise and improve electrical characteristics of the stacked semiconductor package.
Regarding claim 2, Jang further discloses that a width of the first upper pad (PS, Fig. 2) is greater than a width of the second lower pad (PAD3, Fig. 2).
Regarding claim 3, Jang further discloses that each of the first upper pad (PS on 120, Fig. 2) and the second upper pad (PS on 220, Fig. 2) includes pad portions (PAD1/PAD2, Fig. 2) horizontally spaced apart from each other, because PAD1 portion and PAD2 portion are laterally spaced apart from each other (Fig. 2) and a connection portion (connection wiring 180, Fig. 2) electrically connecting the pad portions (PAD1 and PAD2, Fig. 2).
Regarding claim 5, Jang further discloses that a diameter of each of the pad portions (PAD1/PAD2, Fig. 2) is greater than a diameter of each of the first through electrode (120, Fig. 2) and the second through electrode (220, Fig. 2), because “in FIG. 5A, it is illustrated that the sizes of the lower bonding pad PAD3 and the connection pad pattern 265 are larger than those of the upper bonding pads PAD1 and PAD2 but are not limited thereto and may be substantially the same or smaller” (emphasis added, [0041]), therefore, the PAD1 and PAD2 by Jang, which correspond to the pad portions in the claimed invention, can have substantially the same size with PAD3, and since a lateral width of PAD3 is greater than a lateral width of the first and second through-electrodes 120/220, a diameter of PAD1 and PAD2 is also greater than a diameter of the first and second through-electrodes 120/220.
Regarding claim 6, Jang further discloses that the first through electrode (120, Fig. 1) and the second through electrode (220, Fig. 1) are each provided in plural (a plurality of 120 and 220, Fig. 1), and wherein an arrangement of the first through electrodes (120, Fig. 1) in the first semiconductor chip (100, Fig. 1) is equal to an arrangement of the second through electrodes (220, Fig. 1) in the second semiconductor chip (200, Fig. 1).
Regarding claim 7, Jang further discloses that the first through electrode (120, Fig. 1) and the second through electrode (220, Fig. 1) are each provided in plural (a plurality of 120 and 220, Fig. 1)
Jang does not explicitly disclose that an arrangement of the first through electrodes in the first semiconductor chip is different from an arrangement of the second through electrodes in the second semiconductor chip.
However, Jeong discloses the semiconductor package including the plurality of semiconductor chips are vertically stacked (Fig. 1b) and each semiconductor chip includes a plurality of through silicon vias (TSV) 18 (Fig. 1b); Jeong further discloses that the TSVs 18 in the lower semiconductor chip are horizontally spaced apart from the TSVs 18 in an upper semiconductor chip in a plan view (Fig. 1b), therefore, Jeong teaches an arrangement of through electrodes or vias in lower semiconductor chip is different from an arrangement of through electrodes or vias in upper semiconductor chip in a plan view.
Since both Jang and Jeong teach a semiconductor package structure, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the vertically aligned through-electrodes of Jang to be horizontally offset in a plan view, as disclosed by Jeong, in order to reduce electrical noise and improve electrical characteristics of the stacked semiconductor package.
Regarding claim 9, Jeong further discloses that the second semiconductor chip (middle semiconductor chip 10b, Fig. 1b) exposes a portion of the upper surface of the first semiconductor chip (lower semiconductor chip 10a, Fig. 1b), because a leftmost portion of upper surface of the lower semiconductor chip 10a by Jeong is exposed (Fig. 1b).
Regarding claim 10, Jang further discloses that a side surface of the first semiconductor chip (side surface of 100, Fig. 1) and a side surface of the second semiconductor chip (side surface of 200, Fig. 1) are vertically aligned (Fig. 1).
Claims 4 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over by Jang (US 2022/0130799, Foreign priority: Oct. 27, 2020 (KR)) in view of Jeong et al. (KR 20110028746, hereinafter Jeong) as applied to claim 1, and further in view of Wu (CN 210052731). The teachings of Jang in view of Jeong are discussed above.
Regarding claim 4, Jang in view of Jeong does not explicitly disclose that a width of the connection portion is equal to or smaller than a diameter of each of the pad portions.
However, Wu discloses a semiconductor package including a multi-layer chip structure (Fig. 13) having a plurality of through-silicon vias (TSV) 301 in a lower chip and 306 in an upper chip, and therefore, TSV 301 and TSV 306 can correspond to the first through electrode and TSV 306 corresponds to the second through electrode in the claimed invention, respectively; Wu further discloses that the bottom conductive layer 314 is disposed on an upper surface of the TSV 301 and electrically connected to TSV 306, therefore, the bottom conductive layer 314 by Wu corresponds to the first upper pad in the claimed invention; because Applicants do not specifically claim what dimensions the pad portions and connection portion have, the Merriam-Webster dictionary defines a word “portion” as “an often limited part of a whole”, and therefore, different parts of the bottom conductive layer 314 can be selected as two pad portions (left and right portions) and connection portion between two pad portions, as shown in the attached Fig. 13 of Wu below; in this case, a width of the middle portion is smaller than a diameter of each of left and right portions (Fig. 13 below) as claimed.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the configuration of contact pad disposed on the through electrodes in Jang such that a width of middle portion of the contact pad can be smaller than a diameter of another portion of the contact pad, as disclosed by Wu, in order to reduce electrical noise and improve electrical characteristics of the stacked semiconductor package.
PNG
media_image1.png
787
1430
media_image1.png
Greyscale
Regarding claim 8, Jang in view of Jeong differs from the claimed invention by not showing that the first upper pad includes a first region and a second region horizontally spaced apart from the first region, wherein the first through electrode vertically overlaps the first region of the first upper pad, and wherein the second through electrode vertically overlaps the second region of the first upper pad.
However, Wu discloses a semiconductor package including a multi-layer chip structure (Fig. 13) having a plurality of through-silicon vias (TSV) 301 in a lower chip and 306 in an upper chip, and therefore, TSV 301 and TSV 306 can correspond to the first through electrode and TSV 306 corresponds to the second through electrode in the claimed invention, respectively; Wu further discloses that the bottom conductive layer 314 is disposed on an upper surface of the TSV 301 and electrically contacted to TSV 306, therefore, the bottom conductive layer 314 by Wu corresponds to the first upper pad in the claimed invention; because Applicants do not specifically claim what dimensions the first and second regions have, the Merriam-Webster dictionary defines a word “region” as “an indefinite area of the world or universe”, therefore, different and indefinite areas of the bottom conductive layer 314 can be selected as a first region and second region; as shown in the attached Fig. 13 of Wu above, an area on the left side can correspond to the first region in the claimed invention and an area on the right side can correspond to the second region in the claimed invention; in this case, the first region and second region of 314 are horizontally spaced apart from each other, and TSV 301 vertically overlaps the first region and TSV 306 vertically overlaps the second region (Fig. 13 above) as claimed, therefore, Wu teaches an arrangement of through electrodes or vias in each stacked semiconductor chip vertically overlap different, laterally spaced regions of a contact pad.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the arrangement of through electrodes of Jang such that the through electrode are laterally offset on the contact pad, as disclosed by Wu, in order to reduce electrical noise and improve electrical characteristics of the stacked semiconductor package.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WOO K LEE whose telephone number is (571)270-5816. The examiner can normally be reached Monday - Friday, 8:30 am - 5:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JOSHUA BENITEZ can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/WOO K LEE/Examiner, Art Unit 2815
Prosecution Insights