Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. DETAILED ACTION Claims 1-20 are pending and have been examined. Priority Acknowledgment is made of applicant's claim for foreign benefit based on KR10-2023-0040723 filed on 03/28/2023 . Claim Rejections - 35 USC § 102 The following is a quotation of 35 U.S.C. 102(a)(1) that forms the basis for the rejection set forth in this Office action: (a) NOVELTY; PRIOR ART.—A person shall be entitled to a patent unless— (1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention; Notes : when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as ( 30A ; Fig 2B; [0128]) = (element 30A ; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document. Claims 1-9, 16-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chun et al. (US 20190131228 A1 – hereinafter Chun ). R egarding Claim 1, Chun teaches a semiconductor package ( see the entire document; Fig s. 1-2 ; specifically , ([00 21 ] - [004 9 ]), and as cited below ), comprising: a redistribution structure including: an insulating layer ( {400, 310} – Fig. 1 A – [0023] ) defining an upper surface of the redistribution structure ( upper surface of 400 ) and a lower surface ( lower surface of 310 ) of the redistribution structure; a plurality of redistribution layers ( {380, 345} – [0040] ) disposed within the insulating layer ({400, 310} ) ; a recess (seen in Fig. 1A) extending from the upper surface into the insulating layer (400) and exposing at least a portion of a first uppermost redistribution layer among the plurality of redistribution layers ({380, 345} ) ; and a first pad structure ( { 480 , 530} – [0021] ) disposed on a bottom of the recess and an inner wall of the recess (as seen in Fig. 1A) , the first pad structure defining a cavity (CV) that is open upwardly (as seen in Fig. 1A) ; a semiconductor chip ( 50 0 – [0021] ) disposed on the upper surface of the redistribution structure, and including a connection terminal ( 510 – [0048] ) electrically connected to the plurality of redistribution layers (as seen in Fig. 1A) ; a connection bump ( 520 – [0048] ) disposed within the cavity, and electrically connecting the connection terminal (510) of the semiconductor chip and the first pad structure (480 , 530 ) of the redistribution structure to each other; and an encapsulant ( 49 0 – as it is non-conductive – [0049] ) covering at least a portion of the semiconductor chip (lower portion of 500) . Regarding Claim 2 , Chun teaches t he semiconductor package of claim 1, wherein a height from the upper surface of the insulating layer to the bottom of the recess is greater than a height from the upper surface of the insulating layer to an upper surface of the first uppermost redistribution layer (Fig. 1A teaches this limitation) . Regarding Claim 3 , Chun teaches t he semiconductor package of claim 1, wherein the inner wall of the recess has a lower region defined by a side surface of the first uppermost redistribution layer and an upper region defined by the insulating layer on an upper surface of the first uppermost redistribution layer (Fig. 1A teaches this limitation) . Regarding Claim 4 , Chun teaches t he semiconductor package of claim 3, wherein a maximum width of the upper region is greater than a maximum width of the lower region (Fig. 1A teaches this limitation) . Regarding Claim 5 , Chun teaches t he semiconductor package of claim 3, wherein an inclination angle of the lower region with respect to the bottom of the recess is greater than an inclination angle of the upper region with respect to the bottom of the recess (Fig. 1A teaches this limitation) . Regarding Claim 6 , Chun teaches t he semiconductor package of claim 1, wherein the recess comprises a first side defined by the first uppermost redistribution layer and the insulating layer on an upper surface of the first uppermost redistribution layer, and a second side defined only by the insulating layer (Fig. 1A teaches this limitation) . Regarding Claim 7 , Chun teaches t he semiconductor package of claim 6, wherein the first side and the second side are asymmetrical with respect to each other about a center line of the first pad structure (Structure in Fig. 1A is analogous to Fig. 7A of submitted to Drawings) . Regarding Claim 8 , Chun teaches t he semiconductor package of claim 1, wherein the connection bump fills a space between the connection terminal and the first pad structure, and an inside of the cavity (Fig. 1A teaches this limitation) . Regarding Claim 9 , Chun teaches t he semiconductor package of claim 1, wherein the first pad structure comprises: a first conductive layer (460) extending along the upper surface of the insulating layer, the bottom of the recess, and the inner wall of the recess; a second conductive layer (470) disposed on the first conductive layer; and a third conductive layer (530) disposed on the second conductive layer . Regarding Claim 1 6 , Chun teaches a semiconductor package ( see the entire document; Figs. 1-2; specifically, ([0021] - [0049]), and as cited below ), comprising: a redistribution structure including: an insulating layer ({400, 310} – Fig. 1A – [0023]) defining an upper surface of the redistribution structure (upper surface of 400) and a lower surface of the redistribution structure (lower surface of 310) ; a plurality of redistribution layers ({380, 345} – [0040]) disposed within the insulating layer ({400, 310}) ; and a pad structure ({480, 530} – [0021]) extending into the insulating layer (400) from the upper surface and connected to at least a portion of an uppermost redistribution layer among the plurality of redistribution layers ({380, 345}) , the pad structure defining a cavity that is open upwardly (seen in Fig. 1A0 ; a semiconductor chip (500 – [0021]) disposed on the redistribution structure, and including a connection terminal electrically connected to the plurality of redistribution layers; and a connection bump (520 – [0048]) disposed on the pad structure, and electrically connecting the connection terminal (510 – [0048]) of the semiconductor chip and the pad structure (480, 530) to each other, wherein a lower surface of the connection bump is lower than an upper surface of the uppermost redistribution layer (as seen in Fig. 1A) . Regarding Claim 1 7 , Chun teaches t he semiconductor package of claim 16, wherein the uppermost redistribution layer comprises a landing portion including a through-hole, and wherein the pad structure and the connection bump are disposed within the through-hole (Fig. 1A teaches this limitation) . Regarding Claim 1 8 , Chun teaches t he semiconductor package of claim 16, wherein a height of the cavity is greater than a height from an upper surface of the pad structure to the connection terminal (Fig. 1A teaches this limitation) . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Notes : when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as ( 30A ; Fig 2B; [0128]) = (element 30A ; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Chun in view of Kuo et al. (US 20240047552 A1 - hereinafter Kuo ). Regarding Claim 1 0 , Chu n teaches claim 9 from which claim 10 depends. But Chun does not expressly disclose t he semiconductor package of claim 9, wherein the first conductive layer comprises titanium (Ti), the second conductive layer comprises copper (Cu), and the third conductive layer comprises nickel (Ni). However, it is well known in the art to form conductors made of titanium, copper or nickel as is also taught by Kuo (Kuo – [0072]). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the forming conductive layers of titanium, copper or nickel as taught by Kuo into Chun . An ordinary artisan would have been motivated to integrate Kuo structure into Chan structure in the manner set forth above for, at least, for obvious benefits of their well-known conductive properties. Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Chun . Regarding claim 15 , Chun teaches claim 1 from which claim 15 depends. But Chun does not expressly disclose wherein a distance between a lower surface of the semiconductor chip on which the connection terminal is disposed and the upper surface of the insulating layer is about 20 µm or less . The instant application specification contains no disclosure of either the critical nature of the claimed relative thickness i.e., “ wherein a distance between a lower surface of the semiconductor chip on which the connection terminal is disposed and the upper surface of the insulating layer is about 20 µm or less ” or of any unexpected results arising therefrom. Applicant has not disclosed that having wherein a distance between a lower surface of the semiconductor chip on which the connection terminal is disposed and the upper surface of the insulating layer is about 20 µm or less , solves any stated problem or is for any particular purpose. "Where the issue of criticality is involved, the applicant has the burden of establishing his position by a proper showing of the facts upon which he relies." - In re Scherl , 156 F.2d 72, 74-75, 70 USPQ 204, 205 (CCPA 1946), see MPEP 2144.05.III.A. Claims 1 9 is rejected under 35 U.S.C. 103 as being unpatentable over Chun in view of Liu et al. (US 20230307251 A1 - hereinafter Liu ). Regarding claim 19, Chun teaches claim 16 from which claim 19 depends. But Chun does not expressly disclose t he semiconductor package of claim 16, wherein the connection bump comprises tin (Sn) or an alloy of tin (Sn). However, it is well known in the art to form a connection bump of tin as is also taught by Liu (Liu – [0102]). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the forming of a connection bump of tin as is taught by Liu into Chun . An ordinary artisan would have been motivated to integrate Liu structure into Chan structure in the manner set forth above for, at least, for obvious benefits of their well-known conductive properties. Allowable Subject Matter Claim s 11-1 4 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is the Examiner’s Reasons for Allowance : The prior art fails to disclose and would not have rendered obvious : Regarding claim 11 : The semiconductor package of claim 9, wherein an intermetallic compound layer is disposed at an interface between the third conductive layer and the connection bump. Regarding claim 1 2 : The semiconductor package of claim 1, wherein the redistribution structure further comprises: a second pad structure including a pad portion disposed on the upper surface; and a via portion extending into the insulating layer from the pad portion and connected to a second uppermost redistribution layer among the plurality of redistribution layers. Claim s 13-14 depend from claim 12. REASON FOR ALLOWANCE Claim 20 allowed over prior art. Chun teaches some of the limitations of claim 20 as shown in the rejection of claim 1, but not the limitations of “ wherein a first distance from the first sidewall to a center line of the pad structure is shorter than a second distance from the second sidewall to the center line of the pad structure ” as recited in claim 20 . Therefore, the claim 20 is deemed patentable over the prior art . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD A. RAHMAN whose telephone number is (571) 270-0168 and email is mohammad.rahman5@uspto.gov. The examiner can normally be reached on Mon-Fri 8:00-5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice . If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached on (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOHAMMAD A RAHMAN/ Primary Examiner, Art Unit 2898