DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Display Device that Includes Transistors with an Insulating Layer with a Valley Therebetween.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-5, 8-12, and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Jeong et al (US 2017/0294450) in view of Youn et al (US 2016/0118451).
Regarding Claim 1, Jeong et al discloses a display device (display device [0060] Fig 16) comprising:
a substrate (substrate 11 [0061] Fig 16);
a scan line (scan line SL [0118] Fig 18) disposed on the substrate (11 Fig 16) and extending in a first direction (horizontal d1 direction Fig 18);
a data line (data line DL [0118] Fig 18) disposed on the substrate (11 Fig 16) and extending in a second direction (vertical d2 direction Fig 18) crossing the first direction (horizontal direction d1 Fig 18);
a first transistor (second switching element TR2 [0144] Fig 19) disposed on the substrate (11 Fig 16) and comprising a first semiconductor layer (second semiconductor pattern 130b [0144] Fig 19) and a first gate electrode (second gate electrode [0143] Fig 19) overlapping the first semiconductor layer (130b Fig 19);
a second transistor (third switching element TR3 [0125] Fig 18) comprising a second semiconductor layer (third semiconductor pattern 130c [0144] Fig 19) electrically connected to the first transistor (TR2) and the data line (DL), and a second gate electrode (third gate electrode GE3 [0143] Fig 19) overlapping the second semiconductor layer (130c Fig 19) and electrically connected to the scan line (SL Fig 18);
at least one inorganic insulating layer (second insulating film 21 [0074] Fig 16, which may be an inorganic insulator [0074]) disposed on the substrate (11 Fig 2); and
an auxiliary transistor (first switching element TR1 [0144] Fig 19) disposed at an opposite side to the second transistor (TR3), wherein the auxiliary transistor (TR1) is electrically connected to the data line (DL) and the scan line (SL).
Jeong et al does not directly disclose
an auxiliary transistor disposed at an opposite side to the second transistor with a valley defined in the at least one inorganic insulating layer therebetween.
Youn et al, in the related art of semiconductor devices that include flexible organic light emitting display devices, discloses
a valley (hole patterns H1b [0095] Fig 2B) defined in the at least one insulating layer (insulating layers 240, 250, 260 [0096] Fig 2B) between transistors (thin film transistor TFT [0093] Fig 2B).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Jeong et al to include a valley defined in the at least one inorganic insulating layer as taught by Youn et al in order to more efficiently suppress cracks due to folding and the slip phenomenon [0095]. Further, a person of ordinary skill in the art would have recognized that the prevention of cracks would be advantageous in improving the durability and reliability of the device (see MPEP 2143.I(D)).
Regarding Claim 2, the combination of Jeong et al and Youn et al discloses the limitations of claim 1 as explained above. The combination of Jeong et al and Youn et al further discloses
wherein the auxiliary transistor (TR1 Jeong et al) comprises an auxiliary semiconductor layer (first semiconductor pattern 130a [0144] Fig 18 Jeong et al) disposed at an opposite side to the second semiconductor layer (130c Fig 18 Jeong et al) with the valley therebetween (hole patterns H1b [0095] Fig 2B Youn et al) and an auxiliary gate electrode (first gate electrode GE1 [0137] Fig 18 Jeong et al) electrically connected to the scan line (SL Jeong et al) and overlapping the auxiliary semiconductor layer (130a Jeong et al).
Regarding Claim 3, the combination of Jeong et al and Youn et al discloses the limitations of claim 2 as explained above. The combination of Jeong et al and Youn et al further discloses
further comprising: a first connection line (first storage line RL1 [0130] shown in annotated Fig 19 Jeong et al) configured to electrically connect the data line (DL Jeong et al) and the auxiliary semiconductor layer (first semiconductor pattern 130a [0144] Fig 18 Jeong et al) to each other,
the first connection line (RL1 shown in annotated Fig 19 Jeong et al) overlapping the valley (hole patterns H1b [0095] Fig 2B Youn et al); and
a second connection line (line corresponding to first contact hole CNT1 and second contact hole CNT2 [0111] shown in annotated Fig 19 Jeong et al) configured to electrically connect the auxiliary semiconductor layer (130a Jeong et al) and the first semiconductor layer (second semiconductor pattern 130b [0144] Fig 19 Jeong et al) to each other, the second connection line (line corresponding to CNT1 and CNT2 shown in annotated Fig 19 Jeong et al) overlapping the valley (H1b Youn et al).
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Regarding Claim 4, the combination of Jeong et al and Youn et al discloses the limitations of claim 3 as explained above. The combination of Jeong et al and Youn et al further discloses
wherein the first connection line (RL1 shown above in annotated Fig 19 Jeong et al) and the second connection line (line corresponding to CNT1 and CNT2 shown above in annotated Fig 19 Jeong et al) comprise a same material (RL1 may be disposed on the same layer as the scan line SL and may be formed of the same material as the scan line SL which may be formed of aluminum [0138]-[0139]/first electrode 10, second electrode 20, and third electrode 10 may comprise aluminum [0064]-[0076] Fig 17 Jeong et al).
Regarding Claim 5, the combination of Jeong et al and Youn et al discloses the limitations of claim 3 as explained above. The combination of Jeong et al and Youn et al further discloses
wherein the first connection line (RL1 shown above in annotated Fig 19 Jeong et al) and the second connection line (line corresponding to CNT1 and CNT2 shown above in annotated Fig 19 Jeong et al) comprise a same material (RL1 may be disposed on the same layer as the scan line SL and may be formed of the same material as the scan line SL which may be formed of aluminum [0138]-[0139]/first electrode 10, second electrode 20, and third electrode 10 may comprise aluminum [0064]-[0076] Fig 17 Jeong et al) as the scan line (RL1 shown above in annotated Fig 19 Jeong et al).
Regarding Claim 8, the combination of Jeong et al and Youn et al discloses the limitations of claim 2 as explained above. The combination of Jeong et al and Youn et al further discloses
wherein the auxiliary semiconductor layer (130 Jeong et al) comprises a same material (semiconductor layer 130 may comprise an oxide semiconductor and/or amorphous silicon/polycrystalline silicon or the like, and semiconductor layer 130 may include first to third semiconductor patterns 130a, 130b, 130c [0144]-[0145] Jeong et al) as the second semiconductor layer (130c Jeong et al).
Regarding Claim 9, the combination of Jeong et al and Youn et al discloses the limitations of claim 1 as explained above. The combination of Jeong et al and Youn et al further discloses
further comprising an organic insulating material (third insulating film 31 (may be organic) [0109] Fig 16 Jeong et al) at least partially filling the valley (hole patterns H1b [0095] Fig 2B Youn et al).
Regarding Claim 10, Jeong et al discloses a display device (display device [0060] Fig 16) comprising:
a first sub-pixel circuit area (second sub-pixel portion SPX2 [0117] Fig 18) and a second sub-pixel circuit area (first sub-pixel portion SPX1 [0117] Fig 18) arranged adjacent to each other;
a scan line (scan line SL [0118] Fig 18) extending in a first direction (horizontal d1 direction Fig 18) and passing through the first sub-pixel circuit area (SPX2) and the second sub-pixel circuit area (SPX1);
a data line (data line DL [0118] Fig 18) extending in a second direction (vertical d2 direction Fig 18) crossing the first direction (horizontal d1 direction Fig 18) and passing through the first sub-pixel circuit area (SPX2);
a first transistor (third switching element TR3 [0125] Fig 18) comprising a first semiconductor layer (third semiconductor pattern 130c [0144] Fig 19) disposed in the first sub-pixel circuit area (SPX2) and a first gate electrode (third gate electrode GE3 [0143] Fig 19) overlapping the first semiconductor layer (130c);
a second transistor (second switching element TR2 [0144] Fig 19) comprising a second semiconductor layer (second semiconductor pattern 130b [0144] Fig 19) disposed in the first sub-pixel circuit area (SPX2) and electrically connected to the first transistor (TR3) and the data line (DL), and a second gate electrode (second gate electrode [0143] Fig 19) overlapping the second semiconductor layer (130b) and electrically connected to the scan line (SL); and
an auxiliary transistor (first switching element TR1 [0144] Fig 19) comprising an auxiliary semiconductor layer (first semiconductor pattern 130a [0144] Fig 18) disposed in the second sub-pixel circuit area (SPX1) and an auxiliary gate electrode (first gate electrode GE1 [0137] Fig 18) overlapping the auxiliary semiconductor layer (130a), wherein the auxiliary transistor (TR1) is electrically connected to the data line (DL) and the scan line (SL).
Jeong et al does not directly disclose
a valley disposed between the first sub-pixel circuit area and the second sub-pixel circuit area and defined in at least one inorganic insulating layer.
Youn et al, in the related art of semiconductor devices that include flexible organic light emitting display devices, discloses
a valley (hole patterns H1b [0095] Fig 2B) defined in the at least one insulating layer (insulating layers 240, 250, 260 [0096] Fig 2B) between transistors (thin film transistor TFT [0093] Fig 2B).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Jeong et al to include a valley between the first sub-pixel circuit area and the second sub-pixel circuit area and defined in the at least one inorganic insulating layer as taught by Youn et al in order to more efficiently suppress cracks due to folding and the slip phenomenon [0095]. Further, a person of ordinary skill in the art would have recognized that the prevention of cracks would be advantageous in improving the durability and reliability of the device (see MPEP 2143.I(D)).
Regarding Claim 11, the combination of Jeong et al and Youn et al discloses the limitations of claim 10 as explained above. The combination of Jeong et al and Youn et al further discloses
further comprising: a first connection line (first storage line RL1 [0130] shown in annotated Fig 19 Jeong et al) configured to electrically connect the data line (DL Jeong et al) and the auxiliary semiconductor layer (first semiconductor pattern 130a [0144] Fig 18 Jeong et al) to each other,
the first connection line (RL1 shown in annotated Fig 19 Jeong et al) overlapping the valley (hole patterns H1b [0095] Fig 2B Youn et al); and
a second connection line (line corresponding to first contact hole CNT1 and second contact hole CNT2 [0111] shown in annotated Fig 19 Jeong et al) configured to electrically connect the auxiliary semiconductor layer (130a Jeong et al) and the first semiconductor layer (second semiconductor pattern 130b [0144] Fig 19 Jeong et al) to each other, the second connection line (line corresponding to CNT1 and CNT2 shown in annotated Fig 19 Jeong et al) overlapping the valley (H1b Youn et al).
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Regarding Claim 12, the combination of Jeong et al and Youn et al discloses the limitations of claim 11 as explained above. The combination of Jeong et al and Youn et al further discloses
wherein the first connection line (RL1 shown above in annotated Fig 19 Jeong et al) and the second connection line (line corresponding to CNT1 and CNT2 shown above in annotated Fig 19 Jeong et al) comprise a same material (RL1 may be disposed on the same layer as the scan line SL and may be formed of the same material as the scan line SL which may be formed of aluminum [0138]-[0139]/first electrode 10, second electrode 20, and third electrode 10 may comprise aluminum [0064]-[0076] Fig 17 Jeong et al).
Regarding Claim 15, the combination of Jeong et al and Youn et al discloses the limitations of claim 10 as explained above. The combination of Jeong et al and Youn et al further discloses
further comprising an organic insulating material (third insulating film 31 (may be organic) [0109] Fig 16 Jeong et al) at least partially filling the valley (hole patterns H1b [0095] Fig 2B Youn et al).
Regarding Claim 16, the combination of Jeong et al and Youn et al discloses the limitations of claim 10 as explained above. The combination of Jeong et al and Youn et al further discloses
wherein the auxiliary semiconductor layer (130a Fig 18 Jeong et al) comprises a same material (may include an oxide semiconductor or amorphous silicon or polycrystalline silicon or the like [0145] Jeong et al) as the second semiconductor layer (130b Fig 18 Jeong et al).
Regarding Claim 17, the combination of Jeong et al and Youn et al discloses the limitations of claim 15 as explained above. The combination of Jeong et al and Youn et al further discloses
further comprising: a first connection line (first storage line RL1 [0130] shown in annotated Fig 19 Jeong et al) configured to electrically connect the data line (DL Jeong et al) and the auxiliary semiconductor layer (first semiconductor pattern 130a [0144] Fig 18 Jeong et al) to each other,
the first connection line (RL1 shown in annotated Fig 19 Jeong et al) overlapping the valley (hole patterns H1b [0095] Fig 2B Youn et al); and
a second connection line (line corresponding to first contact hole CNT1 and second contact hole CNT2 [0111] shown in annotated Fig 19 Jeong et al) configured to electrically connect the auxiliary semiconductor layer (130a Jeong et al) and the first semiconductor layer (second semiconductor pattern 130b [0144] Fig 19 Jeong et al) to each other, the second connection line (line corresponding to CNT1 and CNT2 shown in annotated Fig 19 Jeong et al) overlapping the valley (H1b Youn et al).
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Claims 6-7 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Jeong et al (US 2017/0294450) in view of Youn et al (US 2016/0118451), and in further view of Yoon et al (US 2021/0126082) and Park et al (US 2019/0372057).
Regarding Claim 6, the combination of Jeong et al and Youn et al discloses the limitations of claim 2 as explained above. The combination of Jeong et al and Youn et al does not disclose
further comprising: a first auxiliary scan line comprising the second gate electrode; and
a second auxiliary scan line comprising the auxiliary gate electrode, wherein each of the first auxiliary scan line and the second auxiliary scan line is electrically connected to the scan line.
Yoon et al, in the related art of semiconductor devices that include display devices, discloses
a first auxiliary scan line (SLA [0191] shown in annotated Fig 8) and a second auxiliary scan line (SLA [0191] shown in annotated Fig 8) that are electrically connected to scan lines (SL1 and SL2 [0191] Fig 8).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Jeong et al and Youn et al to include a first auxiliary scan line and a second auxiliary scan line electrically connected to the scan line as taught by Yoon et al in order to use the same driving circuit on the plurality of pixel substrates [0191]. Further, a person of ordinary skill in the art would have recognized that being able to us the same driving circuit would be advantageous in optimizing the electrical functioning capability of the device while minimizing the space used in the device (see MPEP 2143.I(D)).
The combination of Jeong et al, Youn et al, and Yoon et al does not directly disclose
further comprising: a first auxiliary scan line comprising the second gate electrode; and
a second auxiliary scan line comprising the auxiliary gate electrode.
Park et al, in the related art of semiconductor devices that include display devices, discloses
wherein the gate electrode (second gate electrode 1122 [0103] Fig 3) may be formed as a protrusion pattern protruding from the auxiliary scan line (ASL (not shown [0103])).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Jeong et al, Youn et al, and Yoon et al to include wherein a first auxiliary scan line comprising the second gate electrode; and a second auxiliary scan line comprising the auxiliary gate electrode as taught by Park et al in order to optimize the use of material while further improving the electrical performance of the device. Further, a person of ordinary skill in the art would have recognized that having auxiliary scan lines comprising a gate electrode would be advantageous in providing a device with greater electrical function within smaller size parameters which would help meet the smaller size requirements of the device (see MPEP 2143.I(D)).
Regarding Claim 7, the combination of Jeong et al, Youn et al, Yoon et al, and Park et al discloses the limitations of claim 6 as explained above. The combination of Jeong et al, Youn et al, Yoon et al, and Park et al further discloses
wherein the first auxiliary scan line (SLA Yoon et al corresponding to the third gate electrode GE3 [0143] Fig 19 Jeong et al) and the second auxiliary scan line (SLA Yoon et al corresponding to the first gate electrode GE1 [0137] Fig 18 Jeong et al) are spaced apart from each other with the valley (hole patterns H1b [0095] Fig 2B Youn et al) therebetween.
Regarding Claim 13, the combination of Jeong et al and Youn et al discloses the limitations of claim 10 as explained above. The combination of Jeong et al and Youn et al does not disclose
further comprising: a first auxiliary scan line comprising the second gate electrode; and
a second auxiliary scan line comprising the auxiliary gate electrode, wherein each of the first auxiliary scan line and the second auxiliary scan line is electrically connected to the scan line.
Yoon et al, in the related art of semiconductor devices that include display devices, discloses
a first auxiliary scan line (SLA [0191] shown in annotated Fig 8) and a second auxiliary scan line (SLA [0191] shown in annotated Fig 8) that are electrically connected to scan lines (SL1 and SL2 [0191] Fig 8).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Jeong et al and Youn et al to include a first auxiliary scan line and a second auxiliary scan line electrically connected to the scan line as taught by Yoon et al in order to use the same driving circuit on the plurality of pixel substrates [0191]. Further, a person of ordinary skill in the art would have recognized that being able to us the same driving circuit would be advantageous in optimizing the electrical functioning capability of the device while minimizing the space used in the device (see MPEP 2143.I(D)).
The combination of Jeong et al, Youn et al, and Yoon et al does not directly disclose
further comprising: a first auxiliary scan line comprising the second gate electrode; and
a second auxiliary scan line comprising the auxiliary gate electrode.
Park et al, in the related art of semiconductor devices that include display devices, discloses
wherein the gate electrode (second gate electrode 1122 [0103] Fig 3) may be formed as a protrusion pattern protruding from the auxiliary scan line (ASL (not shown [0103])).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Jeong et al, Youn et al, and Yoon et al to include wherein a first auxiliary scan line comprising the second gate electrode; and a second auxiliary scan line comprising the auxiliary gate electrode as taught by Park et al in order to optimize the use of material while further improving the electrical performance of the device. Further, a person of ordinary skill in the art would have recognized that having auxiliary scan lines comprising a gate electrode would be advantageous in providing a device with greater electrical function within smaller size parameters which would help meet the smaller size requirements of the device (see MPEP 2143.I(D)).
Regarding Claim 14, the combination of Jeong et al, Youn et al, Yoon et al, and Park et al discloses the limitations of claim 13 as explained above. The combination of Jeong et al, Youn et al, Yoon et al, and Park et al further discloses
wherein the first auxiliary scan line (SLA Yoon et al corresponding to the third gate electrode GE3 [0143] Fig 19 Jeong et al) and the second auxiliary scan line (SLA Yoon et al corresponding to the first gate electrode GE1 [0137] Fig 18 Jeong et al) are spaced apart from each other with the valley (hole patterns H1b [0095] Fig 2B Youn et al) therebetween.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Jeong et al (US 2017/0294450) in view of Youn et al (US 2016/0118451), and in further view of Kim et al (US 2020/0302840).
Regarding Claim 18, the combination of Jeong et al and Youn et al discloses the limitations of claim 10 as explained above. The combination of Jeong et al and Youn et al does not disclose
further comprising a third transistor disposed in the first sub-pixel circuit area and electrically connected to the first transistor.
Kim et al, in the related art of semiconductor devices that include display panels, discloses
further comprising a third transistor (third transistor M3 [0099] Fig 16D) disposed in the first sub-pixel circuit area (first sub-pixel circuit PXC1_1 [0289]) and electrically connected to the first transistor (first transistor M1 [0099]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Jeong et al and Youn et al to include a third transistor disposed in the first sub-pixel circuit area and electrically connected to the first transistor as taught by Kim et al in order to supply more current to the light emitting elements [0029]. Further, a person of ordinary skill in the art would have recognized that having more transistors in the sub-pixel circuit area would be advantageous in expanding the electrical functional capability of the device and improve the flow of current (see MPEP 2143.I(D)).
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Jeong et al (US 2017/0294450) in view of Youn et al (US 2016/0118451), and Kim et al (US 2020/0302840), and in further view of Cai et al (US 2021/0249449).
Regarding Claim 19, the combination of Jeong et al, Youn et al, and Kim et al discloses the limitations of claim 18 as explained above. The combination of Jeong et al, Youn et al, and Kim et al does not directly disclose
wherein the third transistor comprises a third semiconductor layer comprising a different material from the first semiconductor layer and a third gate electrode overlapping the third semiconductor layer.
Cai et al, in the related art of semiconductor devices that include display panels, discloses
wherein the third transistor (first transistor 12 [0108] Fig 20) comprises a third semiconductor layer (first organic area 14 [0109]) comprising a different material (organic material) from the first semiconductor layer (second active layer 261 of the second transistor 26 which may be indium gallium zinc oxide IGZO [0108] Fig 20) and a third gate electrode (first gate 122 [0063] Fig 20) overlapping the third semiconductor layer (14).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Jeong et al, Youn et al, and Kim et al to include wherein the third transistor comprises a third semiconductor layer comprising a different material from the first semiconductor layer and a third gate electrode overlapping the third semiconductor layer as taught by Cai et al in order to increase the bendability of the display panel [0111]. Further, a person of ordinary skill in the art would have recognized that having increased bendability would avoid or reduce bending stress and prevent or slow the spread of a crack if one occurs [0012] (see MPEP 2143.I(D)).
Regarding Claim 20, the combination of Jeong et al, Youn et al, Kim et al, and Cai et al discloses the limitations of claim 19 as explained above. The combination of Jeong et al, Youn et al, Kim et al, and Cai et al further discloses
wherein the first semiconductor layer (261 Fig 20 Cai et al) and the third semiconductor layer (14 Fig 20 Cai et al) are arranged on different layers (shown in Fig 20 Cai et al).
Related Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Na et al (US 2019/0385523) which discloses a display device with a first transistor, a second transistor, a third transistor, and an auxiliary transistor [0009], and Choi et al (US 2019/0027093) which discloses a display device with multiple scan lines and date lines coupled to pixels [0042].
Conclusion
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/D.P.S./Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812