Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of claim(s) to be treated in this office action:
a. Independent: 1 and 11
b. Pending: 1-20
Claims 1-2, 11 and 13 have been amended.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 5-10 are rejected under 35 U.S.C. 103 as being unpatentable over Inukai (US 20110193594) in view of Takayanagi et al. (US 9337825).
Regarding independent claim 1, Inukai discloses a transceiver (Fig. 4 and [0036]-[0044]) comprising:
a first inverter chain configured to deliver a signal in response to an enable signal (path 502; Fig. 4 in response to signal EN); and
a second inverter chain coupled to the first inverter chain in parallel (path 501; Fig. 4) and configured to output a reset value of the signal in response to an inverted enable signal (Fig. 4 and [0039]-[0040] describes reset mechanism in response to inverted enable signal ENB),
wherein either the first inverter chain or the second inverter chain operates for delivering the signal based on the enable signal and the inverted enable signal (Fig. 4 shows two chains 501 and 502 operates based on EN and ENB).
Further, Takayanagi teaches an enable signal and an inverted enable signal (Fig. 7 and (66)-(68) describes two different inverter chains and signals Enable 0 and Enable 1 to activate those two chains. Since signal Enable 1 is asserted based on predetermined condition, here Examiner takes note that predetermined condition could be inverted signal Enable 0);
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Takayanagi to Inukai in order to provide with mechanism for more delay elements activated in parallel, more power switches activated at a given time, thereby increasing the overall rate at which power switches are activated as taught by Takayanagi (12).
Regarding claim 2, Inukai and Takayanagi together disclose all the elements of claim 1 as above and through Inukai further a reset circuit configured to reset the signal which is input to the first inverter chain and the second inverter chain, wherein the second inverter chain outputs the reset value while the first inverter chain does not operate (Fig. 4 and [0039]-[0040] describes reset circuit).
Regarding claim 3, Inukai and Takayanagi together disclose all the elements of claim 2 as above and through Inukai further the reset circuit resets the signal in response to the inverted enable signal (Fig. 4 and [0039]-[0040] describes that inverted Enable signal (“ENB”) will reset the device).
Regarding claim 5, Inukai and Takayanagi together disclose all the elements of claim 1 as above and through Inukai further the first inverter chain and the second inverter chain individually comprise a same number of inverters which are connected in series (Fig. 4 shows same number of inverters connected in series in both chains).
Regarding claim 6, Inukai and Takayanagi together disclose all the elements of claim 5 as above and through Inukai further the first and second inverter chains includes a same number of stages, each stage comprising an inverter (Fig. 4 shows each inverter equivalent to a stage), and wherein two inverters of a same stage in the first and second inverter chains have common input and output (Fig. 4 shows first two inverters from two chains are connected to common input and outputs are connected to ground).
Regarding claim 7, Inukai and Takayanagi together disclose all the elements of claim 1 as above and further each inverter included in the first inverter chain is coupled to each of power-gating transistors controlled by the enable signal (Fig. 4 of Inukai and Fig. 7 of Takayanagi together describes the prescribed scenario).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Takayanagi to modified Inukai in order to provide with mechanism for more delay elements activated in parallel, more power switches activated at a given time, thereby increasing the overall rate at which power switches are activated as taught by Takayanagi (12).
Regarding claim 8, Inukai and Takayanagi together disclose all the elements of claim 1 as above and further each inverter included in the second inverter chain is coupled to each of transistors controlled by the inverted enable signal (Fig. 4 of Inukai and Fig. 7 of Takayanagi).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Takayanagi to modified Inukai in order to provide with mechanism for more delay elements activated in parallel, more power switches activated at a given time, thereby increasing the overall rate at which power switches are activated as taught by Takayanagi (12).
Regarding claim 9, Inukai and Takayanagi together disclose all the elements of claim 1 as above and through Inukai further a synchronization circuit configured to receive outputs of the first inverter chain and the second inverter chain and output the signal in response to a synchronization signal (Fig. 4 and [0041] shows sequential circuit 80 that receives outputs from both inverter chains).
Inukai doesn’t disclose a synchronization signal;
However, Takayanagi teaches a synchronization signal (Fig. 1 and (26) describes a synchronizing BE_Clk signal).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Takayanagi to modified Inukai in order to provide with mechanism for more delay elements activated in parallel, more power switches activated at a given time, thereby increasing the overall rate at which power switches are activated as taught by Takayanagi (12).
Regarding claim 10, Inukai and Takayanagi together disclose all the elements of claim 1 as above and through Takayanagi further an inverter included in the second inverter chain is configured to have a slower operation speed than an inverter included in the first inverter chain ((69) describes predetermined time from the assertion of the first enable signal to the assertion of the second enable signal for fast case or a slow case).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Takayanagi to modified Inukai in order to provide with mechanism for more delay elements activated in parallel, more power switches activated at a given time, thereby increasing the overall rate at which power switches are activated as taught by Takayanagi (12).
Claims 11-14 and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lewis et al. (US 20200303325I in view of Inukai (US 20110193594) in view of Takayanagi et al. (US 9337825) and Song et al. (US 20140131895).
Regarding independent claim 11, Lewis discloses a memory system (Fig. 24) comprising:
plural memory dies configured to store data ([0050] describes memory devices); and
a memory controller (Fig. 24 and [0142] describes processor 2402 coupled to a touchscreen controller 2404) coupled to the plural memory dies (Fig. 24 and [0142] describes memory 2406) via a common channel and configured to control the plural memory dies,
wherein at least one of the plural memory dies and the controller comprises a transceiver comprising: a first inverter chain configured to deliver a signal in response to an enable signal; and a second inverter chain coupled to the first inverter chain in parallel and configured to output a reset value of the signal in response to an inverted enable signal, and wherein either the first inverter chain or the second inverter chain operates for delivering the signal based on the enable signal and the inverted enable signal (Inukai and Takayanagi together disclose these limitations in independent device claim 1 and henceforth rejected the same way).
Further, Song explicitly teaches plural memory dies configured to store data (Fig. 1); and
a memory controller (Fig. 1 shows controller 110) coupled to the plural memory dies (Fig.1 shows multiple memory dies R1-R3) via a common channel and configured to control the plural memory dies (Fig. 1 shows common channel 1),
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Inukai, Takayanagi and Song to Lewis in order to provide with a semiconductor integrated circuit as taught by Inukai ([0003]) and to provide with a memory system which includes a memory controller; in order to provide with mechanism for more delay elements activated in parallel, more power switches activated at a given time, thereby increasing the overall rate at which power switches are activated as taught by Takayanagi (12) and a plurality of first semiconductor dies connected with the memory controller through a common channel and configured to operate in response to control signals of the memory controller as taught by Song ([0015]).
Regarding claim 12, Lewis, Inukai, Takayanagi and Song together disclose all the elements of claim 12 as above and through Song further the signal is input or output via the common channel (Fig. 1 shows common channel CH1 as bidirectional).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Song to modified Lewis in order to provide with a memory system which includes a memory controller; and a plurality of first semiconductor dies connected with the memory controller through a common channel and configured to operate in response to control signals of the memory controller as taught by Song([0015]).
Claims 13-14, 16-17 and 19-20 recite the exact same limitations of device claim 2-3, 5-6 and 9-10 respectively and henceforth rejected the same way.
Claim 18 recite the combination of limitations from device claims 7 and 8 and henceforth rejected the same way.
Response to Arguments
Applicant’s arguments with respect to independent claims 1 and 11 have been considered but are moot because the new ground of rejection rely on newly found reference along with previously used reference applied in the prior rejection of record.
New reference Inukai in Fig. 4 and corresponding sections of the Specification describes two inverter chains 501 and 502 are operated by signals ENB and EN which are inverted versions of each other.
Rejections are maintained at-least for above mentioned reasons. Details will be found under “Claim Rejections”
Allowable Subject Matter
Claims 4 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SULTANA BEGUM/Primary Examiner, Art Unit 2824 1/26/2026