Prosecution Insights
Last updated: April 19, 2026
Application No. 18/500,254

SEMICONDUCTOR STRUCTURE WITH CURVED SURFACES

Non-Final OA §102§103
Filed
Nov 02, 2023
Examiner
JOHNSON, CHRISTOPHER A
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Micron Technology, Inc.
OA Round
1 (Non-Final)
84%
Grant Probability
Favorable
1-2
OA Rounds
2y 5m
To Grant
92%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allow Rate
453 granted / 542 resolved
+15.6% vs TC avg
Moderate +9% lift
Without
With
+8.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
23 currently pending
Career history
565
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
50.2%
+10.2% vs TC avg
§102
25.7%
-14.3% vs TC avg
§112
18.9%
-21.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 542 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Election was made traverse in the reply filed on 1/27/2026. The applicant argues that there is no serious search burden, however the examiner will not examine subject matter that requires search in different classification groups. In this case, methods of manufacturing are categorized and searched using quite different search strategies and would involve review of different documents. Applicant has provisionally elected Group II, corresponding to claims 1-10. Invention Group I, corresponding to claims 11-20, is withdrawn from further consideration. The examiner deems the restriction election to be final. Specification The specification submitted 11/02/2023 has been accepted by the examiner. Drawings The drawings submitted on 11/02/2023 have been accepted by the examiner. Information Disclosure Statement The information disclosure statement (IDS) submitted on 11/02/2023 has been considered by the examiner. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-3, 5-10 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Choi (US # 20240064968). Regarding Claim 1, Choi teaches a semiconductor structure, comprising: a patterned material (see structure of Fig. 3 and mapping below) comprising: a plurality of active areas (100, 103A/103B); a first conductive material (XP; [0065] may include a variety of conductive materials) on a surface of each of the active areas; a first metal material (160; [0094]) on a surface of each first conductive materials; a second conductive material (131; [0055]), a third conductive material (132; [0055]), and a first dielectric material (137; [0056]); PNG media_image1.png 611 451 media_image1.png Greyscale a first insulative material (102, 120) separating each active area of the active areas, the first conductive material, and the first metal material from each of the second conductive material, the third conductive material, and the first dielectric material (shown); a curved surface (see annotated figure, circle 1) including a portion of a first side (see recess in the top left side of feature 160) of the first metal material and a portion (especially see the top curved surface of feature 120) of the first insulative material adjacent the first metal material (shown); and a second insulative material (180) and a second metal material (LP) on the surface of the patterned material, wherein a portion of the second insulative material (shown) is in contact with the curved surface, and wherein the second insulative material is different from the first insulative material ([0103] landing pad separation pattern 180 may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxycarbonitride layer, and/or a silicon carbonitride layer versus [0070] feature 120: spacer liner 121, the first spacer 122, and the second spacer 123 may include the same material, for example, silicon oxide). Regarding Claim 2, Choi teaches the semiconductor structure of claim 1, comprising an angled surface (see annotated figure, circle 2) formed in each first insulative material on a second side (right side) of the first metal material. Regarding Claim 3, Choi teaches the semiconductor structure of claim 2, wherein the second metal material is in contact with the angled surface formed in each first insulative material on the second side of the first metal material. Regarding Claim 5, Choi teaches the semiconductor structure of claim 1, wherein the first metal material is a titanium nitride material ([0094]). Regarding Claim 6, Choi teaches the semiconductor structure of claim 1, wherein the third conductive material is a digit line material (feature 132 is part of the BL, which is equivalent to a digit line). Regarding Claim 7, Choi teaches the semiconductor structure of claim 1, wherein the second conductive material serves as an isolation material (feature 131, physically separates, and thus isolates other features). Regarding Claim 8, Choi teaches the semiconductor structure of claim 1, wherein the first insulative material is a nitride material (spacer liner 121 may include silicon nitride). Regarding Claim 9, Choi teaches the semiconductor structure of claim 1, wherein the second insulative material is an oxide material ([0103] feature 180 may include a silicon oxide layer). Regarding Claim 10, Choi teaches the semiconductor structure of claim 1, wherein the active area is a silicon-based material ([0044]). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Choi (US # 20240064968). Regarding Claim 4, Choi does not explicitly disclose that the curved surface has a width greater than 8 nm. However, the width of the curved region would have been a result-effective variable determined by the etching and deposition processes used to form the structure. It would have been obvious to one of ordinary skill in the art to adjust process parameters to obtain a curved surface having a width greater than 8 nm in order to optimize device reliability and reduce electric field concentration. See In re Peterson, 315 F.3d 1325 (Fed. Cir. 2003). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20240324182 A1 Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A JOHNSON whose telephone number is (571)272-9475. The examiner can normally be reached normally working Monday to Friday between 9 am and 6 pm Eastern Time. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached on (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTOPHER A JOHNSON/ Primary Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Nov 02, 2023
Application Filed
Mar 05, 2026
Non-Final Rejection — §102, §103
Apr 14, 2026
Applicant Interview (Telephonic)
Apr 14, 2026
Examiner Interview Summary

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604470
MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
2y 5m to grant Granted Apr 14, 2026
Patent 12604471
SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE
2y 5m to grant Granted Apr 14, 2026
Patent 12598742
Memory Array Comprising Strings Of Memory Cells And Method Used In Forming A Memory Array Comprising Strings Of Memory Cells
2y 5m to grant Granted Apr 07, 2026
Patent 12598751
SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME
2y 5m to grant Granted Apr 07, 2026
Patent 12592281
SEMICONDUCTOR DEVICES AND ELECTRONIC SYSTEMS INCLUDING THE SAME
2y 5m to grant Granted Mar 31, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
84%
Grant Probability
92%
With Interview (+8.6%)
2y 5m
Median Time to Grant
Low
PTA Risk
Based on 542 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month