DETAILED ACTION
This Office Action is in response to Applicant’s application 18/500,311 filed November 2, 2023 in which claims 1 to 20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The Information Disclosure Statement (IDS), filed on November 2, 2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein has been considered by the Examiner.
Drawings
The drawings submitted on November 2, 2023 have been reviewed and accepted by the Examiner.
Priority
Receipt is acknowledged of paper submitted under 35 U.S.C. 119(a)-(d) or under 35 U.S.C. 120, 121, 365(c), or 386(c) which has been placed of record in the file.
Notation
References to patents will be in the form of [C:L] where C is the column number and L is the line number. References to pre-grant patent publications will be to the paragraph number in the form of [xxxx].
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 4-5, 8-11, 14 and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. 2017/0207199 (Kira) and U.S. 2020/0098719 (Park).
Regarding claim 1 Kira discloses at annotated Figure 26 a semiconductor package comprising:
a base chip, e.g. 104A [0005], including upper pads, 111A [0005], on an
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upper surface, as annotated;
a first semiconductor chip, 104B [0005], on the base chip, as shown, the first semiconductor chip including first front pads, 111b [0005], on a first front surface, as annotated and shown, first back pads, as annotated, on a first back surface, as annotated and shown, and first through-vias, 13 [0046] as shown in Figure 1, electrically connecting the first front pads and the first back pads to each other, as shown;
first bump structures, 112 [0005] as annotated, on the first front surface of the first semiconductor chip, as shown, the first bump structures electrically connecting the first front pads and the upper pads to each other, as shown;
a plurality of second semiconductor chips, 104C-104F [0005], sequentially stacked on the first semiconductor chip, as shown, the plurality of second semiconductor chips including second front pads, 111C [0005], on a second front surface, as annotated and shown, second back pads, as annotated, on a second back surface, as shown, and second through-vias, as annotated, electrically connecting the second front pads and the second back pads to each other, as shown;
second bump structures, as annotated, on the second front surface of each of the plurality of second semiconductor chips, as annotated and shown, the second bump structures electrically connecting at least some pads facing each other among the first back pads, the second front pads, and the second back pads, as shown;
adhesive layers, 102 [0005, 45], respectively on the second front surfaces of the plurality of second semiconductor chips, as shown, the adhesive layers surrounding the second bump structures, as shown; and
wherein the adhesive layers respectively have a width equal to or less than a width of the first semiconductor chip and a width of each of the plurality of second semiconductor chips in a direction, parallel to the upper surface of the base chip, as shown.
Kira does not disclose explicitly teach a base chip including lower pads on a lower surface, and through-electrodes electrically connecting the lower pads and the upper pads to each other; and an encapsulant surrounding the first bump structures between the base chip and the first semiconductor chip, the encapsulant covering at least a portion of each of the first semiconductor chip and the plurality of second semiconductor chips.
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Park is directed to semiconductor packaging uses a plurality of semiconductor chips. Referring to annotated Figure 5, Park teaches Kira’s device incorporates a base substrate, i.e. a base chip 300 [0038, 69], including upper pads, 330 [0068] and lower pads 320 [0068] with a through via connecting 320 and 330 as described at [0069]. Park also teaches an encapsulant, 180 [0072], surrounding the first bump structures, 170A [0075], between the base chip and the first semiconductor chip, as shown, the encapsulant covering at least a portion of each of the first semiconductor chip and the plurality of second semiconductor chips, as shown.
Taken as a whole the prior art is directed to semiconductor packages using stacked integrated circuits. Park teaches that Kira’s device may be integrated on to a base substrate 300 which may service as a carrier during the manufacturing process [0097]. Further that the base substrate provides connection terminals, 340, between the package and an external device [0070]. An artisan would find it desirable to configure a semiconductor package for integration and use with an external device, e.g., a PCB. Park also teaches the molding member, 180, serves as an appropriate passivation structure for the package and in particular preventing the intrusion of moisture [0078]. An artisan would recognize the need to chemically and mechanically protect the semiconductor chips from environmental conditions. An artisan would recognize that EMC over-molding is commonly used in semiconductor manufacturing to provide chemical and mechanical protection for the integrated circuits thus improving the reliability of the packaged die.
Accordingly it would have been obvious to a person of ordinary skill in the art at the time of Applicant’s invention to configure the device of claim 1 wherein a base chip includes lower pads on a lower surface, and through-electrodes electrically connecting the lower pads and the upper pads to each other, as taught by Park to integrate the package with an external device as taught by Park; and an encapsulant surrounding the first bump structures between the base chip and the first semiconductor chip, the encapsulant covering at least a portion of each of the first semiconductor chip and the plurality of second semiconductor chips, as taught by Park, to provide for mechanical and chemical protection of the semiconductor chips and improve package reliability, and because the combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
Regarding claim 4 which depends upon claim 1, Park teaches the encapsulant is in contact with side surfaces of the adhesive layers, a first side surface of the first semiconductor chip, and second side surfaces of the plurality of second semiconductor chips.
Regarding claim 5 which depends upon claim 1, Park teaches the adhesive layers include an insulating material layer and fillers in the insulating material layer at [0049].
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Regarding claim 8 which depends upon claim 1, Kira and Park side surfaces of the adhesive layers have an inclination with respect to a first back surface of the first semiconductor chip, e.g. 90 degrees for Kira and less than 90 degrees for Park, see Figure 2.
Regarding claim 9 which depends upon claim 8, Park teaches an angle between the side surfaces of the adhesive layers and the first back surface of the first semiconductor chip is 90° or less at annotated Figure 2.
Regarding claim 10 which depends upon claim 8, Kira teaches an angle between the side surfaces of the adhesive layers and the first back surface of the first semiconductor chip is 90° or more.
Regarding claim 11 which depends upon claim 1, Examiner takes the position that duplication of parts has not patentable weight absent a showing of an unexpected result, see MPEP 2144. Accordingly, configuring the device of claim 1 further comprising: a third semiconductor chip on the plurality of second semiconductor chips, the third semiconductor chip including third front pads on a third front surface; third bump structures on the third front surface of the third semiconductor chip, the third bump structures electrically connecting the third front pads and the second back pads to each other; and an additional adhesive layer on the third front surface of the third semiconductor chip, the additional adhesive layer surrounding the third bump structures is a species of obviousness, see MPEP 2144.
Regarding claim 14 which depends upon claim 1, Park teaches the base chip has a width wider than a width of the first semiconductor chip and a width of each of the plurality of second semiconductor chips in a direction parallel to the upper surface of the base chip at Figure 5.
Regarding claim 16 and referring to the discussion above, Kira discloses a semiconductor package comprising:
a base chip, 104A [0005];
a first semiconductor chip, 104B [0005], on the base chip, as shown;
first bump structures, 112B [0005], electrically connecting the base chip and the first semiconductor chip to each other, as shown;
a second semiconductor chip, 104C [0005], on the first semiconductor chip, as shown;
second bump structures, 112C [0005], electrically connecting the first semiconductor chip and the second semiconductor chip to each other, as shown;
a first adhesive layer, 102 [0005, 0045], surrounding the second bump structures below the second semiconductor chip, as shown;
wherein the first side surface of the first semiconductor chip, the second side surface of the second semiconductor chip, and the side surface of the first adhesive layer are coplanar with each other, as shown.
Kira does not disclose an encapsulant surrounding the first bump structures below the first semiconductor chip, the encapsulant covering a first side surface of the first semiconductor chip, a second side surface of the second semiconductor chip, and a side surface of the first adhesive layer.
Park teaches Kira’s device with an encapsulating layer resulting in an encapsulant, 180 [0072], surrounding the first bump structures, 170A [0075], below the first semiconductor chip, 100A [0022], the encapsulant covering a first side surface of the first semiconductor chip, as shown, a second side surface of the second semiconductor chip 100B [0022] and a side surface of the first adhesive layer, 150 [0022], as shown.
Taken as a whole, the prior art is directed to packaging stacked die. Park teaches the use of an encapsulation layer for stacked die configurations. An artisan would recognize the utility of an encapsulation layer to provide chemical and mechanical protection from environmental conditions.
Accordingly, it would have been obvious to a person of ordinary skill in the art at the time of Applicant’s invention to configure the device of claim 16 with an encapsulating layer resulting in an encapsulant surrounding the first bump structures below the first semiconductor chip, the encapsulant covering a first side surface of the first semiconductor chip, a second side surface of the second semiconductor chip, and a side surface of the first adhesive layer, as taught by Park, to provide chemical and mechanical protection for the semiconductor device as taught by Park and because the combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
Regarding claim 17 which depends upon claim 16, Kira teaches the first adhesive layer entirely overlaps the first semiconductor chip and the second semiconductor chip in a vertical direction.
Regarding claim 18 which depends upon claim 16, Kira teaches a third semiconductor chip, 104D, on the second semiconductor chip, 104C, the third semiconductor chip having a third side surface covered by the encapsulant, resulting from Park’s encapsulation; third bump structures electrically, 112 [0005], connecting the second semiconductor chip and the third semiconductor chip to each other, as shown; and a second adhesive layer, 102, surrounding the third bump structures below the third semiconductor chip, as shown, wherein a side surface of the second adhesive layer is coplanar with the first side surface of the first semiconductor chip, the second side surface of the second semiconductor chip, the side surface of the first adhesive layer, and the third side surface of the third semiconductor chip, as shown.
Regarding claim 19 and referring to the discussion above, Kira discloses a semiconductor package comprising:
a base chip, 104A [0005];
a plurality of semiconductor chips, 104B-F [0005], sequentially stacked on the base chip, as shown;
bump structures, 112C-F [0005], between the base chip and a lowermost semiconductor chip among the plurality of semiconductor chips, the bump structures between the plurality of semiconductor chips; at least one adhesive layer, 102 [0005, 45], surrounding some bump structures, as shown, among the bump structures between the plurality of semiconductor chips, as shown;
Kira does not teach an encapsulant surrounding some bump structures, among the bump structures, between the base chip and the lowermost semiconductor chip, the encapsulant in direct contact with a side surface of each of the plurality of semiconductor chips and a side surface of the at least one adhesive layer.
Park teaches an encapsulant, 180 [0072], surrounding some bump structures, 170 [0075], among the bump structures, between the base chip, 300, and the lowermost semiconductor chip, 100A, the encapsulant in direct contact with a side surface of each of the plurality of semiconductor chips, as shown, and a side surface of the at least one adhesive layer, as shown.
Taken as a whole the prior art is directed to semiconductor packaging. An artisan would find it desirable to protect the semiconductor devices from mechanical and chemical damage. Park teaches and encapsulation structure that protects the device from moisture. An artisan would recognize EMC as a conventional structure to provide mechanical and chemical protection for the semiconductor die.
Accordingly it would have been obvious to a person of ordinary skill in the art at the time of Applicant’s invention to configure the device of claim 19 with an encapsulant surrounding some bump structures, among the bump structures, between the base chip and the lowermost semiconductor chip, the encapsulant in direct contact with a side surface of each of the plurality of semiconductor chips and a side surface of the at least one adhesive layer, to provide mechanical and chemical protection for the semiconductor die and because the combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
Regarding claim 20 which depends upon claim 19, Kira teaches the side surface of each of the plurality of semiconductor chips and the side surface of the at least one adhesive layer are coplanar with each other.
Allowable Subject Matter
Claim 2-3, 6-7, 12-13 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2 the prior art fails to disclose the device of claim 1, wherein a first distance between the base chip and the first semiconductor chip is greater than a second distance between the first semiconductor chip and a lowermost second semiconductor chip, among the plurality of second semiconductor chips where Examiner is mindful of the burden of production and persuasion.
Claim 3 depends upon claim 2 and is allowable on that basis.
Regarding claim 6 the prior art fails to disclose the device of claim 5, wherein at least one of the fillers protrude from side surfaces of the adhesive layers and is in contact with the encapsulant.
Regarding claim 7 the prior art fails to disclose the device of claim 5, wherein at least one of the fillers is removed from side surfaces of the adhesive layers, defining a recess in the insulating material layer contacting the encapsulant.
Regarding claim 12 the prior art fails to disclose the device of claim 11, wherein a third back surface of the third semiconductor chip is exposed from the encapsulant.
Regarding claim 13 the prior art fails to disclose the device of claim 11, wherein the third semiconductor chip has a thickness greater than a thickness of the first semiconductor chip and a thickness of each of the plurality of second semiconductor chips.
Regarding claim 15 the prior art fails to disclose the device of claim 1, wherein lengths of the upper pads of the base chip in a vertical direction and lengths of the first front pads of the first semiconductor chip in the vertical direction are different from each other.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is listed on the notice of references cited.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Joe Schoenholtz whose telephone number is (571)270-5475. The examiner can normally be reached M-Thur 7 AM to 7 PM PST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ms. Yara Green can be reached at (571) 272-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.E. Schoenholtz/Primary Examiner, Art Unit 2893