DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The disclosure is objected to because of the following informalities:
Page 18, paragraph 66, line 6: Change “passed” to “past”.
Appropriate correction is required.
Claim Objections
Claims 1-10 are objected to because of the following informalities:
Claim 1, line 1: Change the colon at the end of the line to a semi-colon.
Claims 2-10 are objected to for depending from objected-to base claim 1.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 9 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Lim, U.S. Pat. Pub. No. 2021/0036121, Figures 1 and 2.
PNG
media_image1.png
358
319
media_image1.png
Greyscale
PNG
media_image2.png
399
523
media_image2.png
Greyscale
Regarding claim 1: Lim Figures 1 and 2 disclose a semiconductor device (1000a) comprising: a substrate (10)[;] an active pattern (105) on the substrate (101); a first source/drain pattern (middle left (150) in Figure 2, I-I’ cross-section) and a second source/drain pattern (middle right (150) in Figure 2, I-I’ cross-section), which overlap with the active pattern (105); a separation insulating layer (200a) between the first source/drain pattern (middle left (150)) and the second source/drain pattern (middle right (150)); and a first gate electrode (middle left (165)) and a second gate electrode (middle right (165)) which are spaced apart from each other with the separation insulating layer (200a) interposed therebetween, wherein a level of a top surface of the separation insulating layer (200a) is higher than a level of a top surface of the first gate electrode (middle left (165)) and a level of a top surface of the second gate electrode (middle right (165)). Lim specification ¶¶ 31-63.
Regarding claim 9, which depends from claim 1: Lim discloses a bottom surface of the separation insulating layer (200a) is disposed in the active pattern. Id. ¶ 58 (“In an example embodiment of the present inventive concept, the lower end of the isolation structure 200a may tie [sic, likely “be”] disposed to be lower than lower ends of the source/drain regions 150 and higher than a lower end of the active region 105, but the dispositions are not limited thereto.”).
Claims 19 and 20 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Liang, U.S. Pat. Pub. No. 2024/0105805, Figures 1A to 2O-3.
PNG
media_image3.png
428
691
media_image3.png
Greyscale
PNG
media_image4.png
418
710
media_image4.png
Greyscale
Regarding claim 19: Liang Figures 1A to 2O-3 disclose a semiconductor device (100) comprising: a substrate (102 in Liang Figure 1A) including an active pattern (104B-W (Liang Figure 1B): 104-3, 104-4); first source/drain patterns (150-3) overlapping the active pattern (104B-W (Liang Figure 1B): 104-3, 104-4); second source/drain patterns (150-4) overlapping the active pattern (104B-W (Liang Figure 1B): 104-3, 104-4); a first channel pattern (108’-3) between the first source/drain patterns (150-3); a second channel pattern (108’-4) between the second source/drain patterns (150-4); a first gate electrode (168-3) between the first source/drain patterns (150-3); a second gate electrode (168-4) between the second source/drain patterns (150-4); and a separation insulating layer (190: 118’, 120, 121, 124’, 192, 194) between the first source/drain patterns (150-3) and the second source/drain patterns (150-4), wherein each of the first channel pattern (108’-3) and the second channel pattern (108’-4) comprises semiconductor patterns overlapping with each other in a vertical direction. Liang specification ¶¶ 38-100.
Regarding claim 20, which depends from claim 19: Liang discloses the first and second gate electrodes (168-3, 168-4) are spaced apart from each other with the separation insulating layer (190: 118’, 120, 121, 124’, 192, 194) interposed therebetween, and wherein the first and second channel patterns (108’-3, 108’-4) are spaced apart from each other with the separation insulating layer (190: 118’, 120, 121, 124’, 192, 194) interposed therebetween. See Liang Figure 2O-1.
Claims 1-3 and 9 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Jang, U.S. Pat. Pub. No. 2025/0142906, Figures 1-8.
PNG
media_image5.png
468
868
media_image5.png
Greyscale
PNG
media_image6.png
461
809
media_image6.png
Greyscale
PNG
media_image7.png
469
878
media_image7.png
Greyscale
PNG
media_image8.png
421
878
media_image8.png
Greyscale
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Regarding claim 1: Jang Figures 1-8 disclose a semiconductor device comprising: a substrate (100)[;] an active pattern (AP) on the substrate (100); a first source/drain pattern (left (150)) and a second source/drain pattern (right (150)) which overlap with the active pattern (AP); a separation insulating layer (200, 206) between the first source/drain pattern and the second source/drain pattern; and a first gate electrode (left (GS)) and a second gate electrode (right (GS)) which are spaced apart from each other with the separation insulating layer (portion (200) of separation insulating layer (200, 206)) interposed therebetween, wherein a level of a top surface of the separation insulating layer (200, 206) is higher than a level of a top surface of the first gate electrode (left (GS)) and a level of a top surface of the second gate electrode (right (GS)). Jang specification ¶¶ 30-159.
Regarding claim 2, which depends from claim 1: Jang discloses a first active contact (left (190)) on the first source/drain pattern (left (150)), wherein the level of the top surface of the separation insulating layer (200, 206) is substantially the same as a level of a top surface of the first active contact (left (190)). See Jang Figure 5.
Regarding claim 3, which depends from claim 2: Jang discloses a second active contact (right (190)) on the second source/drain pattern (right (150)), wherein the level of the top surface of the separation insulating layer (200, 206) and the level of the top surface of the first active contact (left (190)) are substantially the same as a level of a top surface of the second active contact (right (190)). See id.
Regarding claim 9, which depends from claim 1: Jang discloses a bottom surface of the separation insulating layer (200, 206) is disposed in the active pattern (AP). See id.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 3, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Lim.
Regarding claim 2, which depends from claim 1: Lim discloses a first active contact (180) on the first source/drain pattern (middle left (150)), wherein the level of the top surface of the separation insulating layer (200a) is lower than a level of a top surface of the first active contact (middle left (180)). See Lim Figure 2. Lim does not disclose that the level of the top surface of the separation insulating layer is substantially the same as a level of a top surface of the first active contact. However, the disclosure does not indicate the significance of the level of the top surface of the separation insulating layer being substantially the same as a level of a top surface of the first active contact. The purpose of the first active contact is to make an electrical connection and the purpose of the separation insulating layer is to separate and insulate the two source/drain patterns from one another. Because the claim requirement is not patentably significant, claim 2 is rejected as an obvious variant over the prior art.
Regarding claim 3, which depends from claim 2: Lim discloses a second active contact (middle right (180)) on the second source/drain pattern (middle right (150)), wherein the level of the top surface of the separation insulating layer (200a) is below the level of a top surface of the second active contact (middle right (180)), and the level of the top surface of the first active contact (middle left (180) is substantially the same as a level of a top surface of the second active contact (middle right (180)). See id. Lim does not disclose that the level of the top surface of the separation insulating layer is substantially the same as a level of a top surface of the second active contact. However, as with claim 2’s requirements, the disclosure does not indicate the significance of the level of the top surface of the separation insulating layer being substantially the same as a level of a top surface of the second active contact. The purpose of the second active contact is to make an electrical connection and the purpose of the separation insulating layer is to separate and insulate the two source/drain patterns from one another. Because the claim requirement is not patentably significant, claim 3 is rejected as an obvious variant over the prior art.
Regarding claim 10, which depends from claim 1: Lim discloses semiconductor patterns (140) connected to the first source/drain pattern (middle left (150)), wherein the first gate electrode (middle left (165)) includes: interposed portions between the semiconductor patterns (140); and a plug portion connected to the interposed portions. Lim specification ¶ 37. Lim does not disclose that the interposed portions include a conductive material different from that of the plug portion. However, applicants’ disclosure does not indicate the patentable significant of the interposed portions including a conductive material different from that of the plug portion. The purpose of the plug portion and the interposed portions is to provide conductivity for the gate to function, and this can be done with the same conductive materials as well as different conductive materials. Because the claim requirement is not patentably significant, claim 10 is rejected an obvious variant over the prior art.
Claims 1, 9, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Liang.
Regarding claim 1: Liang Figures 1A to 2O-3 disclose a semiconductor device (100) comprising: a substrate (102)[;] an active pattern (104B-W (Liang Figure 1B): 104-3, 104-4) on the substrate (102); a first source/drain pattern (150-3) and a second source/drain pattern (150-4) which overlap with the active pattern (104B-W (Liang Figure 1B): 104-3, 104-4); a separation insulating layer (190: 118’, 120, 121, 124’, 192, 194) between the first source/drain pattern (150-3) and the second source/drain pattern (150-4); and a first gate electrode (168-3) and a second gate electrode (168-4) which are spaced apart from each other with the separation insulating layer (190: 118’, 120, 121, 124’, 192, 194) interposed therebetween, wherein a level of a top surface of the separation insulating layer (190: 118’, 120, 121, 124’, 192, 194) is at a same level as a level of a top surface of the first gate electrode (168-3) and a level of a top surface of the second gate electrode (168-4). Liang does not disclose that a level of a top surface of the separation insulating layer is higher than a level of a top surface of the first gate electrode and a level of a top surface of the second gate electrode. Liang specification ¶¶ 38-100. However, this feature is due to the process by which the device is made. The process limitation of how a layer is formed has no patentable weight in claims drawn to structure. Note that a product-by-process claim is directed to the product per se, not the process by which the product is made. In re Hirao, 190 USPQ 15 at 17 n. 3 (CCPA 1976). See also In re Brown, 173 USPQ 685, 688 (CCPA 1972); In re Luck, 177 USPQ 523, 525 (CCPA 1973); In re Fessman, 180 USPQ 324, 325-26 (CCPA 1974); In re Avery, 186 USPQ 161, 166-67 (CCPA 1975); In re Wertheim, 191 USPQ 90, 103 (CCPA 1976); and In re Marosi, 218 USPQ 289, 292-93 (Fed. Cir. 1983), all of which make it clear that it is the patentability of the final product per se which must be determined in a product-by-process claim, and not the patentability of the process, and that an old or obvious product by a new method is not patentable as a product, whether claimed in product-by-process claims or not. Note that the applicant has the burden of proof in such cases, according to case law.
Regarding claim 9, which depends from claim 1: Liang discloses a bottom surface of the separation insulating layer (190: 118’, 120, 121, 124’, 192, 194) is disposed in the active pattern (104B-W (Liang Figure 1B): 104-3, 104-4). See Liang Figure 2O.
Regarding claim 10, which depends from claim 1: Liang discloses semiconductor patterns (108’-3) connected to the first source/drain pattern (150-3), wherein the first gate electrode (168-3) includes: interposed portions between the semiconductor patterns (108-3’); and a plug portion connected to the interposed portions, and wherein the interposed portions include a conductive material same as that of the plug portion. See Liang Figure 2O-1. Liang does not disclose that the interposed portions include a conductive material different from that of the plug portion. However, applicants’ disclosure does not indicate the patentable significant of the interposed portions including a conductive material different from that of the plug portion. The purpose of the plug portion and the interposed portions is to provide conductivity for the gate to function, and this can be done with the same conductive materials as well as different conductive materials. Because the claim requirement is not patentably significant, claim 10 is rejected an obvious variant over the prior art.
Allowable Subject Matter
Claims 11-18 are allowed.
Claims 4-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if the informality in claim 1 were addressed.
The following is a statement of reasons for the indication of allowable subject matter:
With regard to claim 4: The claim has been found allowable because the prior art of record does not disclose “a lower insulating pattern separating the first source/drain pattern from the active pattern, wherein a sidewall of the lower insulating pattern is in direct contact with a sidewall of the separation insulating layer”, in combination with the remaining limitations of the claim.
With regard to claims 5-8: The claims have been found allowable due to their dependency from claim 4 above.
With regard to claim 11: The claim has been found allowable because the prior art of record does not disclose “a gate separation pattern in direct contact with the first and second gate electrodes, wherein the gate separation pattern separates the first and second gate electrodes from each other”, in combination with the remaining limitations of the claim.
With regard to claims 12-18: The claims have been found allowable due to their dependency from claim 11 above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTORIA KATHLEEN HALL whose telephone number is (571)270-7567. The examiner can normally be reached Monday-Friday, 8 a.m.-5 p.m.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached at 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Victoria K. Hall/Primary Examiner, Art Unit 2897