DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 5-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Okita et al. (U.S. Patent No. 9,917,092).
Regarding to claim 1, Okita teaches a wafer comprising (Fig. 8B illustrates upper layers of Fig. 1D after the gaps in layer 20 are formed and filled):
a silicon layer (Fig. 1, Fig. 8B, element 1; column 4, line 16);
a first dielectric layer on the silicon layer (Fig. 1, Fig. 8B, element 15, 16 or 17; column 4, lines 18-19, lines 60-61);
a ferroelectric layer on the first dielectric layer (Fig. 1, Fig. 8B, element 20; column 5, line 25), wherein the ferroelectric layer defines one or more gaps between portions of the ferroelectric layer (Fig. 8B, the ferroelectric layer 20 defines gaps between portions of the ferroelectric layer 20); and
a second dielectric layer on the ferroelectric layer and disposed within the one or more gaps (Fig. 8B, element 31, column 9, lines 42-44).
Regarding to claim 5, Okita teaches an array of die regions separated by dicing lanes (Fig. 8B).
Regarding to claim 6, Okita teaches the one or more gaps are defined along one or more of the dicing lanes (Fig. 8B).
Regarding to claim 7, Okita teaches the one or more gaps are defined within one or more of the die regions (Fig. 8B).
Regarding to claim 8, Okita teaches the one or more gaps relieve stress between the silicon layer and the ferroelectric layer (the gaps formed by dividing the ferroelectric layer into smaller pieces, thus the gaps relieve stress between the silicon layer and the ferroelectric layer).
Regarding to claim 9, Okita teaches the first dielectric layer comprises silicon dioxide (column 4, lines 18-19, lines 60-61).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Okita et al. (U.S. Patent No. 9,917,092) in view of Takaya et al. (U.S. Patent No. 7,371,635).
Regarding to claim 2, Okita does not disclose the wafer comprises a silicon-on-insulator (SOI) series of layers. Hsu discloses a wafer comprises a silicon-on-insulator (SOI) series of layers (column 3, lines 43-48). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Okita in view of Takaya to use SOI wafer as the substrate in order to control current leakage.
Regarding to claim 3, Takaya discloses the SOI series of layers comprises a silicon substrate, an insulative layer, and a top layer of silicon (Fig. 3, column 3, lines 49-52, the SOI series of layers comprises silicon substrate 33, insulative layer 32, and top layer of silicon 31).
Regarding to claim 4, Takaya discloses insulative layer comprises silicon dioxide (column 3, line 31).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Okita et al. (U.S. Patent No. 9,917,092) in view of Chou et al. (U.S. Patent No. 9,761,683).
Regarding to claim 10, Okita does not disclose second dielectric layer comprises a flowable dielectric material. Chou discloses a dielectric layer comprises a flowable dielectric material (column 3, lines 50-55). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Okita in view of Chou to comprise a flowable dielectric material in the second dielectric layer in order to ensure no voids created in the gaps after filling.
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Okita et al. (U.S. Patent No. 9,917,092) in view of Tsugawa et al. (U.S. Patent No. 10,656,568).
Regarding to claim 11, Okita discloses materials of the ferroelectric layer (column 5, lines 46-50). Okita does not clearly disclose the ferroelectric layer comprises barium titanate. Tsugawa discloses ferroelectric layer comprises barium titanate (column 5, lines 17-19). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Okita in view of Tsugawa to comprise barium titanate in the ferroelectric layer in order to make the system performing in cool environment.
Regarding to claim 12, Okita discloses materials of the ferroelectric layer (column 5, lines 46-50). Okita does not clearly disclose the ferroelectric layer comprises a seed layer of strontium titanate followed by a layer of barium titanate. Tsugawa discloses a seed layer of strontium titanate followed by a layer of barium titanate (column 10, lines 42-46). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Okita in view of Tsugawa to comprise a seed layer of strontium titanate followed by a layer of barium titanate ferroelectric layer in order to make the system performing in cool environment.
Regarding to claim 13, Okita discloses materials of the ferroelectric layer (column 5, lines 46-50). Okita does not clearly disclose the ferroelectric layer comprises a seed layer of strontium titanate followed by a layer of barium strontium titanate. Tsugawa discloses a seed layer of strontium titanate followed by a layer of barium strontium titanate (Table 6A-B, column 10, lines 42-46). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Okita in view of Tsugawa to comprise a seed layer of strontium titanate followed by a layer of barium strontium titanate ferroelectric layer in order to make the system performing in cool environment.
Pertinent Art
For the benefits of the Applicant, US-7518181-B2, US-7696549-B2, US-7541297-B2, US-9076954-B2, and US-10693055-B2, are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. The references fail to disclose the limitations including “a ferroelectric layer on the first dielectric layer, wherein the ferroelectric layer defines one or more gaps between portions of the ferroelectric layer; a second dielectric layer on the ferroelectric layer and disposed within the one or more gaps”, and in combination with the rest of limitations recited the claims.
Conclusion
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/VU A VU/Primary Examiner, Art Unit 2897