DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Acknowledgment is made that applicant's Amendment, filed on June 12th, 2026, has been entered.
Upon entrance of the Amendment, claim 1 was amended. Claims 1-13 are currently pending.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5, and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ozaki (U.S. Patent Application Publication No. 2009/0127602).
Regarding to claim 1, Ozaki teaches a wafer comprising:
a silicon layer having a top surface (Fig. 2, element 10);
a first dielectric layer on the top surface of the silicon layer (Fig. 2, stack ILD);
a ferroelectric layer having a bottom surface on the first dielectric layer (Fig. 2, element FE), wherein the ferroelectric layer defines one or more gaps between portions of the ferroelectric layer (Fig. 2); and
a second dielectric layer on the ferroelectric layer and disposed within the one or more gaps (Fig. 2, element BD).
Regarding to claim 5, Ozaki teaches an array of die regions separated by dicing lanes (only one die illustrated in the figure, however in fabrication process, array of dices are formed on a wafer, the array of dices separated by dicing lanes).
Regarding to claim 8, Ozaki teaches the one or more gaps relieve stress between the silicon layer and the ferroelectric layer (silicon layer and ferroelectric layer have different thermal expansion coefficients, gaps between ferroelectric layer inherently release stress due to thermal mismatch).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Ozaki (U.S. Patent Application Publication No. 2009/0127602) in view of Takaya et al. (U.S. Patent No. 7,371,635).
Regarding to claim 2, Ozaki does not disclose the wafer comprises a silicon-on-insulator (SOI) series of layers. Hsu discloses a wafer comprises a silicon-on-insulator (SOI) series of layers (column 3, lines 43-48). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ozaki in view of Takaya to use SOI wafer as the substrate in order to control current leakage.
Regarding to claim 3, Takaya discloses the SOI series of layers comprises a silicon substrate, an insulative layer, and a top layer of silicon (Fig. 3, column 3, lines 49-52, the SOI series of layers comprises silicon substrate 33, insulative layer 32, and top layer of silicon 31).
Regarding to claim 4, Takaya discloses insulative layer comprises silicon dioxide (column 3, line 31).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Ozaki (U.S. Patent Application Publication No. 2009/0127602) in view of Chou et al. (U.S. Patent No. 9,761,683).
Regarding to claim 10, Ozaki does not disclose second dielectric layer comprises a flowable dielectric material. Chou discloses a dielectric layer comprises a flowable dielectric material (column 3, lines 50-55). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ozaki in view of Chou to comprise a flowable dielectric material in the second dielectric layer in order to ensure no voids created in the gaps after filling.
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Ozaki (U.S. Patent Application Publication No. 2009/0127602) in view of Tsugawa et al. (U.S. Patent No. 10,656,568).
Regarding to claim 11, Ozaki discloses materials of the ferroelectric layer (column 5, lines 46-50). Okita does not clearly disclose the ferroelectric layer comprises barium titanate. Tsugawa discloses ferroelectric layer comprises barium titanate (column 5, lines 17-19). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ozaki in view of Tsugawa to comprise barium titanate in the ferroelectric layer in order to make the system performing in cool environment.
Regarding to claim 12, Ozaki discloses materials of the ferroelectric layer (column 5, lines 46-50). Okita does not clearly disclose the ferroelectric layer comprises a seed layer of strontium titanate followed by a layer of barium titanate. Tsugawa discloses a seed layer of strontium titanate followed by a layer of barium titanate (column 10, lines 42-46). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ozaki a in view of Tsugawa to comprise a seed layer of strontium titanate followed by a layer of barium titanate ferroelectric layer in order to make the system performing in cool environment.
Regarding to claim 13, Ozaki discloses materials of the ferroelectric layer (column 5, lines 46-50). Ozaki does not clearly disclose the ferroelectric layer comprises a seed layer of strontium titanate followed by a layer of barium strontium titanate. Tsugawa discloses a seed layer of strontium titanate followed by a layer of barium strontium titanate (Table 6A-B, column 10, lines 42-46). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ozaki in view of Tsugawa to comprise a seed layer of strontium titanate followed by a layer of barium strontium titanate ferroelectric layer in order to make the system performing in cool environment.
Allowable Subject Matter
Claims 6-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter:
Regarding to claim 6, the prior art fails to anticipate or render obvious the claimed limitations including “the one or more gaps are defined along one or more of the dicing lanes” in combination with the limitations recited in claims 1 and 5.
Regarding to claim 7, the prior art fails to anticipate or render obvious the claimed limitations including “the one or more gaps are defined within one or more of the die regions” in combination with the limitations recited in claims 1 and 5.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VU A VU whose telephone number is (571)270-7467. The examiner can normally be reached M-F: 8:00AM - 5:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD M DICKE can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/VU A VU/Primary Examiner, Art Unit 2897
Prosecution Insights