DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election, with traverse, of Species I of which claims read upon 1-10 in the “Response to Election / Restriction Filed - 04/09/2026”, is acknowledged.
Applicant’s traversal submittal that the search and examination of all the claims may be made without serious burden, or at least claims 17- 20 in addition to claims 1-10” is not persuasive as claims 17-20 is identified as species III as “of a method for manufacturing a semiconductor package described in [0028-0094-0127]” that certainly requires a different field of search (different search strategies or search queries, as evidenced by the above-defined distinctions between the species) (see MPEP § 808.02) and/or the prior art applicable to one species would not likely be applicable to another species; and/or the inventions are likely to raise different non-prior art issues under 35 U.S.C. 101 and/or 35 U.S.C. 112, first paragraph.
Species ii reading of figures 7-8 and of a second embodiment of another semiconductor package described in [0015, 0026-0028+] and characterized by a dummy die instead of a heat dissipation structure of FIG. 1.heat dissipation structure are distinct as well from subject matter of species I and certainly requires a different field of search (different search strategies or search queries, as evidenced by the above-defined distinctions between the species..
The restriction requirement is still deemed proper for non-elected claims 11-20, and is therefore made FINAL, and thus the required provisional election (see MPEP § 818.03(b)) becomes an election without traverse.
In view of the above, this office action considers claims 1-20 pending for prosecution, wherein claims 11-20 are withdrawn from further consideration, and 1-10 are presented for examination
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (3124; Fig 15; [0054]) = (element 124; Figure No. 15; Paragraph No. [0054]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The primary reference citation may not be preceded by the inventor tag, wherein the other reference citation will carry inventor tag. These conventions are used throughout this document.
Claim 1-4 and 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over Yu; Chen-Hua et al., (US 20220344287 A1) hereinafter Yu’287 in view of Tang; Tzu-Chun et al. (US 20230065844 A1); hereinafter Tang.
Regarding claim 1. Yu’287 teaches a semiconductor package (100; annotated Fig 15; [0054]) comprising (see the entire document, fig 15 along with figures and relevant description, specifically as cited below):
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Yu’287 Fig 15 (truncated for illustrating main parts)
a first redistribution layer structure (124; Fig 15; [0064]; detailed in Fig 13 [0049]) including first redistribution lines (140; [0049]);
a first semiconductor structure (150, labelled as dies; Fig 15) on the first redistribution layer structure (124);
a plurality of first conductive posts (at leasr two TDVs 118 at left side of 150) on the first redistribution layer structure (124) and next to a first side (left side) of the first semiconductor structure (150);
a plurality of second conductive posts (at leasr two TDVs 118 at right side of 150) on the first redistribution layer structure (124) and next to a second side (right side of 150) opposite to the first side of the first semiconductor structure (150) ;
a molding material (of 122, first cited in Fig 10; [0043]) molding the first semiconductor structure (150), the plurality of first conductive posts (118 at left side of 150), and the plurality of second conductive posts (118 at right side of 150), on the first redistribution layer structure (124);
a second redistribution layer structure (comprising {60,104, 106, 108, 110}. labelled in Figs 3; [0028]) including second redistribution lines (104) on the molding material;
a second semiconductor structure (50C, plurality) on the second redistribution layer structure (comprising {60,104, 106, 108, 110};
a heat dissipation structure (200, labelled as thermal module and heat sink; Fig 20; [0059]) on the second redistribution layer structure (comprising {60,104, 106, 108, 110}); and
and a 3D solenoid inductor (146) including,
the first redistribution lines (134) at an uppermost portion of the first redistribution layer structure, and
The difference between Yu’287 and claimed 1 is for 3D solenoid inductor (146) including
“some of the plurality of second conductive posts, the second redistribution lines at a lowermost portion of the second redistribution layer structure (comprising {60,104, 106, 108, 110}.
However, in the analogous art, Tang teaches a semiconductor package having a 3D solenoid inductor, and the 3D solenoid inductor therein is formed with portions of a metallization pattern of a front-side redistribution structure, portions of a metallization pattern of a back-side redistribution structure, and through vias connecting the respective metallization patterns( [0013]), wherein (Figs 18-19; [0064-0065]) 3D solenoid inductor IN3 IN3 may include portions of the metallization pattern 332, the conductive pillars 230 and portions of the metallization pattern 312 i.e. IN3 effectively embedded in the first redistribution structure 310, the second redistribution structure 330 and the encapsulant 235 therebetween. In the illustrated embodiment, a projection of the inductor IN3 is located outside a projection of the die stack 200.
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Tang Fig 18
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to adapt the Tang’s configuration for Yu’287’s 3D solenoid inductor, , thereafter, the combination of (Yu’287 and Tang)’s comprises and a 3D solenoid inductor (146) including, a 3D solenoid inductor including, some of the plurality of second conductive posts (Tang), the first redistribution lines (134) at an uppermost portion of the first redistribution layer structure (124), and the second redistribution lines (in view of Tang) at a lowermost portion of the second redistribution layer structure (comprising {60,104, 106, 108, 110}), since this configuration, at least, one or more of the 3D solenoid inductors IN3 may be included in a semiconductor package based on the design requirements.(Tang [0067]).
Regarding claim 2. The combination of (Yu’287 and Tang) as applied to the semiconductor package of claim 1, further teaches; wherein:
the 3D solenoid inductor (146 in view of Tang’s configuration) is electrically connected to the second semiconductor structure (any of 50C) through the second redistribution layer structure ((comprising {60,104, 106, 108, 110}).
Regarding claim 3. The combination of (Yu’287 and Tang) as applied to the semiconductor package of claim 1, further teaches; wherein:
the 3D solenoid inductor (146 in view of Tang’s configuration) is electrically insulated (by mold) from the first semiconductor structure (150) .
Regarding claim 4. The combination of (Yu’287 and Tang) as applied to the semiconductor package of claim 1, Yu’287 further teaches; wherein:
the plurality of first conductive posts (118) are electrically connected (through 120 and 128; fig 12; [0042]) to the first semiconductor structure (150) through the first redistribution layer structure (124A3).
Regarding claim 7. The combination of (Yu’287 and Tang) as applied to the semiconductor package of claim 1, further teaches; wherein:
a region of a footprint of the second semiconductor structure (one of 50C, ar right most; Fig15) and a region of a footprint of the 3D solenoid inductor overlap (in view of Tang IM3; Fig 18).
Regarding claim 8. The combination of (Yu’287 and Tang) as applied to the semiconductor package of claim 1, Yu’287 further teaches; wherein:
a region of a footprint of the heat dissipation structure ((200, labelled as thermal module; Fig 20; [0059])) is included (depicted in Fig 20) within a region of a footprint of the first semiconductor structure (150).
Regarding claim 9. The combination of (Yu’287 and Tang) as applied to the semiconductor package of claim 1, Yu’287 further teaches; wherein:
the heat dissipation structure (200) includes a heat slug (labelled as heat sink, 200; [0059]).
Regarding claim 10. The combination of (Yu’287 and Tang) as applied to the semiconductor package of claim 9, Yu’287 further teaches; (the package) further comprising:
a thermal interface material (TIM 298; Fig 20; [0061]) between the heat slug (heat sink, 200) and the second redistribution layer structure.
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Yu; Chen-Hua et al., (US 20220344287 A1) hereinafter Yu’287; in view of Tang; Tzu-Chun et al. (US 20230065844 A1); hereinafter Tang; and in further view of Kuo; Chien-Li et al. (US 20230377905 A1); hereinafter Kuo.
Regarding claim 5. The combination of (Yu’287 and Tang) as applied to the semiconductor package of claim 1,does not expressly disclose; wherein:
some other second conductive posts among the plurality of second conductive posts are dummy posts.
However, in the analogous art, Kuo teaches an integrated circuit die including a die connector; a first through via adjacent the integrated circuit die; an encapsulant encapsulating the first through via and the integrated circuit die; and a redistribution structure, redistribution line that physically and electrically coupled to the die connector, and electrically isolated from the first through via ([abstract]), wherein (Figs 4-6 ; [0024]) a second subset of the through vias 116 are dummy through vias 116D that are not not be electrically coupled to the subsequently formed overlying redistribution lines, and are not electrically functional.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to adapt the Kuo’s configuration and thereafter, the combination of (Yu’287, Tang and Kuo)’s comprises some other second conductive posts among the plurality of second conductive posts are dummy posts since this configuration, at least, dummy through post 116D suppress thermal expansion of the subsequently formed encapsulant, thereby reducing the risk of the redistribution lines cracking (Kuo [0024]).
Regarding claim 6. The combination of (Yu’287, Tang and Kuo) as applied to the semiconductor package of claim 5, further teaches; wherein:
the dummy posts (Kuo 116D Fig 6) are electrically insulated from the first redistribution layer structure (124) and the second redistribution layer structure (comprising {60,104, 106, 108, 110}).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOAZZAM HOSSAIN whose telephone number is (571)270-7960. The examiner can normally be reached M-F: 8:30AM - 6:00 PM.
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/MOAZZAM HOSSAIN/Primary Examiner, Art Unit 2898
May 1, 2026
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