DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to because Figures 36-46 are in color. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Color photographs and color drawings are not accepted in utility applications unless a petition filed under 37 CFR 1.84(a)(2) is granted. Any such petition must be accompanied by the appropriate fee set forth in 37 CFR 1.17(h), one set of color drawings or color photographs, as appropriate, if submitted via the USPTO patent electronic filing system or three sets of color drawings or color photographs, as appropriate, if not submitted via the via USPTO patent electronic filing system, and, unless already present, an amendment to include the following language as the first paragraph of the brief description of the drawings section of the specification:
The patent or application file contains at least one drawing executed in color. Copies of this patent or patent application publication with color drawing(s) will be provided by the Office upon request and payment of the necessary fee.
Color photographs will be accepted if the conditions for accepting color drawings and black and white photographs have been satisfied. See 37 CFR 1.84(b)(2).
Claim Objections
Claims 5 and 7 are objected to because of the following informalities: the word “portion” should be added after “lower semiconductor gate electrode” in lines 2, respectively. Appropriate correction is required.
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-15, in the reply filed on 04/30/2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites the limitation "the third lateral dimension" in line 3. There is insufficient antecedent basis for this limitation in the claim. Claim 6 depends on claims 4 and 5 which recite “a maximum lateral dimension of the first gate electrode” and “a maximum lateral dimension of the lower semiconductor gate electrode,” respectively. However, there is no recitation or definition of a “third lateral dimension.” It is unclear if this refers to one of the “maximum lateral dimensions” of claims 4 or 5 or another dimension.
For purposes of examination. Claim 6 has been interpreted to mean a lateral dimension of the upper semiconductor gate electrode portion along the second gate electrode direction is greater than the maximum lateral dimension of the lower semiconductor gate electrode along the second gate electrode direction.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-7, and 11 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Matsui et al. (US 2002/0036317).
In reference to claim 1, Matsui et al. (US 2002/0036317), hereafter “Matsui,” discloses a semiconductor structure, comprising:
a first field effect transistor, Figure 41B, comprising a first active region 10 and a first gate electrode that comprises a first semiconductor gate electrode portion 13 (mislabeled as 12 in Figure 41B) paragraphs 75 and 80;
a first trench isolation structure 15 laterally surrounding the first active region;
a second field effect transistor, select gate in Figure 2, comprising a second active region and a second gate electrode that comprises a stack of a lower semiconductor gate electrode portion 13 and an upper semiconductor gate electrode portion 18, paragraph 78;
a second trench isolation structure 15 laterally surrounding the second active region; and
at least one dielectric material layer 19 overlying the first field effect transistor and the second field effect transistor, wherein:
the first semiconductor gate electrode portion contacts sidewall surface segments of the first trench isolation structure 15 and comprises a top surface contacting the at least one dielectric material layer 19, Figure 41B;
the lower semiconductor gate electrode portion 13 has a same material composition and a same thickness as the first semiconductor gate electrode portion 13, and contacts sidewall surface segments of the second trench isolation structure; and
the upper semiconductor gate electrode portion 18 comprises a bottom surface contacting the lower semiconductor gate electrode 13 and top surface segments of the second shallow trench isolation structure.
In reference to claim 3, Matsui discloses the first active region comprises a first source region and a first drain region that are laterally spaced from each other by a first channel along a first channel direction; the first gate electrode laterally extends along a first gate electrode direction that is perpendicular to the first channel direction, Figures 19 and 41; the second active region comprises a second source region and a second drain region that are laterally spaced from each other by a second channel along a second channel direction; and the second gate electrode laterally extends along a second gate electrode direction that is perpendicular to the second channel direction, Figure 1.
In reference to claim 4, Matsui discloses a maximum lateral dimension of the first gate electrode, 13 in Figure 41A, along the first gate electrode direction equals a lateral dimension of a top surface of the first active region 10 along the first gate electrode direction.
In reference to claim 5, Matsui discloses a maximum lateral dimension of the lower semiconductor gate electrode, 13 in selective gate region of Figure 2, along the second gate electrode direction equals a lateral dimension of a top surface of the second active region 10 along the second gate electrode direction.
In reference to claim 6, Matsui discloses a lateral dimension of the upper semiconductor gate electrode portion along the second gate electrode direction is greater than the [maximum lateral dimension of the lower semiconductor gate electrode], selective gate region of Figure 2.
In reference to claim 7, Matsui discloses the upper semiconductor gate electrode portion 18 and the lower semiconductor gate electrode [portion] 13 have a same width along the second channel direction, selective gate region of Figure 3A.
In reference to claim 11, Matsui discloses each sidewall of the first semiconductor gate electrode portion that contacts the sidewall surface segments of the first trench isolation structure has a respective taper angle relative to a vertical plane that is perpendicular to the first gate electrode direction, Figure 41.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Matsui et al. (US 2002/0036317) in view of Kamigaichi et al. (US 2007/0018226).
In reference to claim 8, Matsui discloses the first field effect transistor comprises a first gate dielectric, 12 in Figure 41, overlying the first active region 10 and underlying the first gate electrode, paragraph 114.
Matsui does not disclose two first dielectric gate spacers contacting a respective sidewall of the first gate electrode; and a lateral dimension of the first gate dielectric along the first channel direction equals a width of the first gate electrode along the first channel direction.
Kamigaichi et al. (US 2007/0018226), hereafter “Kamigaichi,” discloses an analogous semiconductor device including teaching two first dielectric gate spacers, 8 in Figure 8 contacting a respective sidewall of the first gate electrode; and a lateral dimension of the first gate dielectric 6 along the first channel direction equals a width of the first gate electrode 4, 7 along the first channel direction, Figure 8.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the semiconductor device to include two first dielectric gate spacers contacting a respective sidewall of the first gate electrode; and a lateral dimension of the first gate dielectric along the first channel direction equals a width of the first gate electrode along the first channel direction. One would have been motivated to do so in order to mask implants for source and drain regions, paragraphs 100 and 110.
In reference to claim 10, Kamigaichi discloses the two first dielectric gate spacers, 8 in Figure 21, are not in direct contact with each other, and have a maximum height that is less than a sum of a thickness of the first gate dielectric 6 and a thickness of the first gate electrode 4, 7, 11, Figure 21.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Matsui et al. (US 2002/0036317) in view of Kamigaichi et al. (US 2007/0018226) as applied to claim 8 above and further in view of Yaegashi et al. (US 2001/0000625).
In reference to claim 9, Matsui discloses the second field effect transistor comprises a second gate dielectric, 12 in Figure 2, overlying the second active region and underlying the lower semiconductor gate electrode portion, paragraph 75.
Matsui does not disclose and two second dielectric gate spacers contacting a respective sidewall of the lower semiconductor gate electrode portion; the second gate dielectric is thicker than the first gate dielectric; and a lateral dimension of the second gate dielectric along the second channel direction equals a width of the second gate electrode along the second channel direction.
Kamigaichi teaches two second dielectric gate spacers, 8 in Figure 7, contacting a respective sidewall of the lower semiconductor gate electrode portion 4; and a lateral dimension of the second gate dielectric 2 along the second channel direction equals a width of the second gate electrode along the second channel direction, paragraphs 100 and 110.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the device to include two second dielectric gate spacers contacting a respective sidewall of the lower semiconductor gate electrode portion; and a lateral dimension of the second gate dielectric along the second channel direction equals a width of the second gate electrode along the second channel direction.
Kamigaichi does not disclose the second gate dielectric is thicker than the first gate dielectric.
Yaegashi et al. (US 2001/0000625) discloses an analogous semiconductor device including teaching a second gate dielectric, 108 in Figure 3, (of select transistor) is thicker than the first gate dielectric 105 of Vcc-Tr, paragraph 87. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the second gate dielectric to be thicker than the first gate dielectric. One would have been motivated to do so in order to integrate formation of different transistors with different switching characteristics, paragraph 90.
Claims 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Matsui et al. (US 2002/0036317) in view of Shimizu et al. (US 2001/0019508).
In reference to claim 12, Matsui does not disclose the first gate electrode has a variable lateral dimension along the first gate electrode direction that decreases with a vertical distance from a horizontal plane including a top surface of the first active region.
Shimizu et al. (US 2001/0019508), hereafter “Shimizu,” disclose an analogous semiconductor device including teaching a first gate electrode, 66, 67 of peripheral transistor in Figure 10, has a variable lateral dimension along the first gate electrode direction that decreases with a vertical distance from a horizontal plane including a top surface of the first active region.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the first gate electrode to have a variable lateral dimension along the first gate electrode direction that decreases with a vertical distance from a horizontal plane including a top surface of the first active region.
One would have been motivated to do so in order to improve the filling of an isolation feature to prevent formation of voids, paragraph 61.
In reference to claim 13, Matsui does not disclose the lower semiconductor gate electrode portion has a variable lateral dimension along the second gate electrode direction that decreases with a vertical distance from a horizontal plane including a top surface of the second active region.
Shimizu teaches a lower semiconductor gate electrode portion, 14a in Figure 1B, has a variable lateral dimension along the second gate electrode direction that decreases with a vertical distance from a horizontal plane including a top surface of the second active region, paragraph 60. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the lower semiconductor gate electrode portion to have a variable lateral dimension along the second gate electrode direction that decreases with a vertical distance from a horizontal plane including a top surface of the second active region.
One would have been motivated to do so in order to improve the filling of an isolation feature to prevent formation of voids, paragraph 61.
In reference to claim 14, Matsu is silent regarding the upper semiconductor gate electrode portion has a uniform lateral dimension along the second gate electrode direction that is invariant with the vertical distance from the horizontal plane including the top surface of the second active region.
Shimizu teaches the upper semiconductor gate electrode portion is “ vertically processed in a self-aligning manner so that the side end portions are aligned,” paragraph 58. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the upper semiconductor gate electrode portion to have a uniform lateral dimension along the second gate electrode direction that is invariant with the vertical distance from the horizontal plane including the top surface of the second active region. To do so would have merely been to combine prior art elements according to known methods to yield predictable results; KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385, (2007). MPEP 2143 I. A. In this case to define and structure the lateral extents of the gate.
Allowable Subject Matter
Claims 2 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 2 would be allowable because the prior art of record fails to teach or fairly suggest the structure comprising wherein the first gate electrode does not include any additional semiconductor gate electrode portion which contacts the first semiconductor gate electrode portion, and the first gate electrode lacks an interface between two semiconductor gate portions; in combination with the other recited limitations in the base claim.
Claim 15 would be allowable because the prior art of record fails to teach or fairly suggest the structure comprising a first gate metal-semiconductor alloy region in contact with a top surface segment of the first semiconductor gate electrode portion; in combination with the other recited limitations in the base claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kato et al. (US 2015/0060994), Lee et al. (US 2007/0108498), Noguchi et al. (US 2006/0220003), Lee (US 2005/0258471), and Ichige et al. (US 2002/0070402) disclose related structures with gate layers overlapping isolation structures.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRYAN R. JUNGE whose telephone number is (571)270-5717. The examiner can normally be reached M-F 8:00-4:30 CT.
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/BRYAN R JUNGE/ Primary Examiner, Art Unit 2897
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