Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/02/2023 and 04/02/2025 is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2,11-13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Prechtl et a, US 20170244407 A1.
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Pertaining to claim 1, Prechtl teaches ( See fig.8 above for example) and para [0005], [0009], [0027] to [0030], [0033] to [0036], and Figs. 3 and 8), a semiconductor device 200 is a semiconductor device 200 capable of preventing unnecessary turning-on of a device. A first field effect transistor 102 (corresponding to "the first transistor”) and a low voltage switching element 118 (corresponding to the “second transistor”) are provided in the semiconductor package 106, and a drain of the low voltage switching element 118 (corresponding to “the first electrode” of the second transistor) is provided. A source of the low voltage switching element 118 (corresponding to "first electrode” of the "second transistor”) is connected to a gate of the first field effect transistor 102 (corresponding to "a control electrode” of the "second transistor”). The point that is connected to the source (corresponding to the "second electrode” of the "first transistor”) of the first field effect transistor 102, and the lead frame 120 is the lead frame. A first gate lead 122, a second gate lead 124, a source lead 126, and a drain lead 128, and a first field effect transistor 102 mounted on the lead frame 120 is a gate disposed on the upper surface of the die 130. The point that the source and drain terminals are provided, and the first bond wire 132 connects the gate terminal of the first field effect transistor 102 and a first gate lead 122 (corresponding to "the first control electrode pin”), and the second bond wire 134 is a bond wire. A gate terminal of the low voltage switching element 118 (corresponding to "a control electrode of the second transistor”) and a second gate lead 124 (corresponding to "a second control electrode pin”) are connected to each other. The third bonding wire 136 connects the drain terminal and the drain lead 126 of the first electric field effect transistor 102, the fourth bonding wire 138 connects the source terminal and the source lead 128 of the first electric field effect transistor 102, and the fifth bonding wire 146 connects the electric field effect transistor. A drain terminal of the low-voltage switching element 118 and a gate terminal of the first field-effect transistor 102 (via a first gate lead 122) are connected to each other. The second die 140 of the low-voltage switching element 118 is mounted on a DBC (direct copper junction) substrate 148 disposed between the lower side of the lead frame 120 and the drain electrode of the source lead 126 (see paragraph [0036], Fig. 8, in particular).
Pertaining to claim 2, Prechtl teaches ( See fig.3 and fig.8 above for example) that both the first field effect transistor 102 and the low voltage switching element 118 are n-type.
Pertaining to claim 11, Prechtl teaches ( See fig.3 and fig.8 above for example) the source lead 126 corresponds to the "first chip mounting portion", and the DBC (direct copper bonding) substrate 148 corresponds to the "second chip mounting portion". Furthermore, the semiconductor package 106 has a high probability of being a "sealing body.
Pertaining to claim 12 and 13, Prechtl teaches ( See fig.3 and fig.8 above for example) the lead frame 120 corresponds to the "first pad," and the upper surface electrode of the DBC (direct copper junction) substrate 148 corresponds to the "third pad.
Allowable Subject Matter
Claims17-20 allowed.
The following is an examiner's statement of reasons for allowance: The closest prior art of record of Prechtl et al, US 20170244407 A1 teaches the limitation of " A semiconductor device, comprising an encapsulation body, a first transistor and a capacitor, wherein the first transistor comprises a control electrode, a first terminal and a second terminal, but it does not teach or suggest, singularly or in combination, at least the limitations of the independent claim 17 including “the capacitor comprises a first capacitor electrode and a second capacitor electrode; the first transistor is configured to allow a current to flow from the first terminal to the second terminal under the control of a potential at the control electrode of the first transistor; the first capacitor electrode is electrically coupled to the control electrode of the first transistor, and the second capacitor electrode is electrically coupled to the second terminal of the first transistor; and the first transistor and the capacitor are encapsulated by the same encapsulation body, and the control electrode of the first transistor is electrically coupled to a first control electrode pin.”
Claims 3-10,14-16 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner's statement of reasons for allowance: The closest prior art of record of Dip (US 2012/0003825 A1) teaches the limitation of claim 1, but it does not teach or suggest, singularly or in combination, at least the limitations of the dependent claim 3 and 8 including “the first semiconductor chip is provided with a first surface and a first back surface opposite to the first surface, and the second semiconductor chip is provided with a second surface and a second back surface opposite to the second surface; a first control electrode pad and a first pad are formed on the first surface of the first semiconductor chip, and the first back surface is electrically coupled to the first terminal of the first transistor; the first control electrode pad is electrically coupled to the control electrode of the first transistor and the first control electrode pad respectively, and the first pad is electrically coupled to the second terminal of the first transistor; a second control electrode pad and a second pad are formed on the first surface of the second semiconductor chip, and the second back surface is electrically coupled to the first electrode of the second transistor; the second control electrode pad is electrically coupled to the control electrode of the second transistor and the second control electrode pin respectively, and the second electrode of the second transistor is electrically coupled to the second pad; the first chip support member is provided with a first upper surface, the first semiconductor chip is supported on the first upper surface of the first chip support member, and the first back surface of the first semiconductor chip faces the first upper surface and is electrically coupled to the first chip support member; and the second chip support member is provided with a second upper surface, the second semiconductor chip is supported on the second upper surface of the second chip support member, and the second back surface of the second semiconductor chip faces the second upper surface and is electrically coupled to the second chip support member” in combination with the remaining limitations of the claim.
The following is an examiner's statement of reasons for allowance: The closest prior art of record of Dip (US 2012/0003825 A1) teaches the limitation of claim 1, but it does not teach or suggest, singularly or in combination, at least the limitations of the dependent claim 14 including “the first semiconductor chip is provided with a first surface and a first back surface opposite to the first surface, and the second semiconductor chip is provided with a second surface and a second back surface opposite to the second surface; a first control electrode pad and a first pad are formed on the first surface of the first semiconductor chip, the first back surface is electrically coupled to the first terminal of the first transistor, the first control electrode pad is electrically coupled to the control electrode of the first transistor and the first control electrode pin respectively, and the first pad is electrically coupled to the second terminal of the first transistor; a second control electrode pad, at least one second pad and at least one third pad are formed on the first surface of the second semiconductor chip, the second control electrode pad is electrically coupled to the control electrode of the second transistor and the second control electrode pin respectively, the second electrode of the second transistor is electrically coupled to the second pad, and the first electrode of the second transistor is electrically coupled to the third pad; the chip support member is provided with an upper surface, the first semiconductor chip is supported on the upper surface of the chip support member, and the first back surface of the first semiconductor chip faces the upper surface and is electrically coupled to the chip support member; and the second semiconductor chip is supported on the upper surface of the chip support member, and the second back surface of the second semiconductor chip faces the upper surface.” in combination with the remaining limitations of the claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO 892.
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/MAMADOU L DIALLO/Primary Examiner, Art Unit 2897