DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to because Figures 36-46 are in color.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Color photographs and color drawings are not accepted in utility applications unless a petition filed under 37 CFR 1.84(a)(2) is granted. Any such petition must be accompanied by the appropriate fee set forth in 37 CFR 1.17(h), one set of color drawings or color photographs, as appropriate, if submitted via the USPTO patent electronic filing system or three sets of color drawings or color photographs, as appropriate, if not submitted via the via USPTO patent electronic filing system, and, unless already present, an amendment to include the following language as the first paragraph of the brief description of the drawings section of the specification:
The patent or application file contains at least one drawing executed in color. Copies of this patent or patent application publication with color drawing(s) will be provided by the Office upon request and payment of the necessary fee.
Color photographs will be accepted if the conditions for accepting color drawings and black and white photographs have been satisfied. See 37 CFR 1.84(b)(2).
Election/Restrictions
Applicant’s election without traverse of Group I, claim 1-15, in the reply filed on 06/15/2026 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 3-10 are rejected under 35 U.S.C. 103 as being unpatentable over Matsui et al. (US 2002/0036317).
In reference to claim 1, Matsui et al. (US 2002/0036317), hereafter “Matsui,” discloses a semiconductor structure, with reference to Figure 19 and 20, comprising:
a first field effect transistor (peripheral transistor) comprising a first active region 10 and a first gate electrode that comprises a first semiconductor gate electrode portion 13 and a first metallic gate electrode portion 18, paragraphs 80, 84, and 115; and wherein:
the first active region comprises a first source region and a first drain region that are laterally spaced from each other by a first channel along a first channel direction (vertical direction in Figures 19 and 20);
the first gate electrode laterally extends along a first gate electrode direction (horizontal direction in Figures 19 and 20) that is perpendicular to the first channel direction; and
a maximum lateral extent of the first metallic gate electrode portion along the first gate electrode direction is greater than a maximum lateral extent of the first semiconductor gate electrode portion along the first gate electrode direction.
Matsui is silent regarding a second field effect transistor comprising a second active region and a second gate electrode that comprises a second semiconductor gate electrode portion and a second metallic gate electrode portion.
The examiner takes OFFICIAL NOTICE that it is well known in the art for the peripheral circuit regions of NAND flash type memory devices such as that disclosed by Matsui to include multiple transistors. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the structure to include a second field effect transistor comprising a second active region and a second gate electrode that comprises a second semiconductor gate electrode portion and a second metallic gate electrode portion. One would have been motivated to do so in order to provide multiple peripheral transistor for the logic circuitry to control a memory array, as suggested by Matsui, paragraph 5.
[AltContent: textbox (1st thickness)][AltContent: textbox (2nd thickness)][AltContent: connector][AltContent: connector]In reference to claim 3, Matsui discloses the first metallic gate electrode portion comprises a center segment, corresponding to opening 17, having a first thickness and peripheral segments having a second thickness that is less than the first thickness, see Figure 19 and annotated Figure 20 below.
In reference to claim 4, Matsui discloses an entirety of the center segment of the first metallic gate electrode portion has an areal overlap with the first semiconductor gate electrode portion in a plan view, Figure 19 and paragraphs 114 and 119.
In reference to claim 5, Matsui discloses an entirety of the peripheral segments of the first metallic gate electrode portion does not have any areal overlap with the first semiconductor gate electrode portion in a plan view, see annotated Figure 20 above.
In reference to claim 6, Matsui discloses wherein top surfaces of the peripheral segments and a top surface of the center segment are located entirely within a horizontal plane (top surface of 18 in Figure 19).
In reference to claim 7, Matsui discloses a first trench isolation structure, 15 in Figure 20, laterally surrounding the first active region; and a second trench isolation structure 15 (of another peripheral transistor) laterally surrounding the second active region, wherein the first metallic gate electrode portion comprises peripheral segments that overlie the first trench isolation structure, see annotated Figure 20 above.
In reference to claim 8, Matsui discloses a center segment of the first metallic gate electrode portion (corresponding to opening 17) having an areal overlap with the first active region has a first thickness; and peripheral segments of the first metallic gate electrode portion having an areal overlap with the first trench isolation structure have a second thickness that is less than the first thickness, see annotated Figure 20 above.
In reference to claim 9, Matsui discloses the peripheral segments of the first metallic gate electrode portion do not have any areal overlap with the first semiconductor gate electrode portion in a plan view, see annotated Figure 20 above.
In reference to claim 10, Matsui discloses the first semiconductor gate electrode portion 13 has an areal overlap with the first active region 10 and does not have any areal overlap with the first trench isolation structure 15 in a plan view, paragraphs 80 and 115.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Matsui et al. (US 2002/0036317) in view of Morin (US 2015/0243784).
In reference to claim 2, Matsui discloses the second active region comprises a second source region and a second drain region that are laterally spaced from each other by a second channel along a second channel direction; the second gate electrode laterally extends along a second gate electrode direction that is perpendicular to the second channel direction, paragraphs 80, 84, and 115.
Matsui does not disclose a maximum lateral extent of the second metallic gate electrode portion along the second gate electrode direction is the same as a maximum lateral extent of the second semiconductor gate electrode portion along the second gate electrode direction.
Morin (US 2015/0243784) discloses an analogous semiconductor device including teaching forming a plurality of transistors with gates less than, equal to, or greater than a size of the active area, paragraph 70. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for a maximum lateral extent of the second metallic gate electrode portion along the second gate electrode direction to be the same as a maximum lateral extent of the second semiconductor gate electrode portion along the second gate electrode direction. To do so would have merely been to combine prior art elements according to known methods to yield predictable results; KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385, (2007). MPEP 2143 I. A. In this case combining transistors with different gate sizes onto a single die.
Claims 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Matsui et al. (US 2002/0036317) in view of Kamigaichi et al. (US 2007/0018226).
In reference to claim 13, Matsui does not disclose a first dielectric gate spacer contacting lengthwise sidewalls of the first semiconductor gate electrode portion, lengthwise sidewalls of the first metallic gate electrode portion, and sidewalls of the first trench isolation structure.
Kamigaichi et al. (US 2007/0018226) discloses an analogous semiconductor device including teaching a first dielectric gate spacer, 8 in Figures 19 and 21, contacting lengthwise sidewalls of the lower gate electrode portion 4, lengthwise sidewalls of the upper gate electrode portion 7, and sidewalls of the first trench isolation structure, paragraphs 111 and 112. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for a first dielectric gate spacer to contact lengthwise sidewalls of the first semiconductor gate electrode portion, lengthwise sidewalls of the first metallic gate electrode portion, and sidewalls of the first trench isolation structure. One would have been motivated to do so in order to mask source/drain ion implantations, paragraph 113.
In reference to claim 14, Kamigaichi discloses wherein the first dielectric gate spacer comprises at least three openings therethrough, wherein: the first gate electrode is located in a first opening of the at least three openings; a first source region 23 of the first field effect transistor underlies a second opening of the at least three openings; and a first drain region 23 of the first field effect transistor underlies a third opening of the at least three openings, Figure 21, paragraphs 112 and 113.
Allowable Subject Matter
Claims 11, 12, and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 11 would be allowable because the prior art of record fails to teach or fairly suggest the structure wherein the first trench isolation structure comprises: a top surface that is located within a same horizontal plane as a top surface of the first metallic gate electrode portion; a recessed horizontal surface that contacts bottom surfaces of the peripheral segments of the first metallic gate electrode portion; and a first widthwise sidewall that connects an edge of the top surface to an edge of the recessed horizontal surface; in combination with the other recited limitations in the base claims.
Claim 12 depends on claim 11 and would be allowable in combination with the other recited limitations in the respective base claims.
Claim 15 would be allowable because the prior art of record fails to teach or fairly suggest the structure wherein the first shallow trench isolation structure comprises a top surface and a recessed horizontal surface that is recessed relative to the top surface; the recessed horizontal surface laterally surrounds the first active region; and an outer dielectric spacer having a same material composition as the first dielectric gate spacer overlies the recessed horizontal surface and sidewalls of the first trench isolation structure that connect the top surface and the recessed horizontal surface.; in combination with the other recited limitations in the base claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Iwase et al. (US 8,241,984), Lee et al. (US 2007/0108498), and Lee (US 2005/0258471), disclose similar gate structures.
Arai et al. (US 2008/0006885), Houston (US 2002/0036347), and Esaki (US 2001/0050396) disclose related isolation structure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRYAN R. JUNGE whose telephone number is (571)270-5717. The examiner can normally be reached M-F 8:00-4:30 CT.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/BRYAN R JUNGE/ Primary Examiner, Art Unit 2897
Prosecution Insights