Prosecution Insights
Last updated: April 19, 2026
Application No. 18/500,797

SEMICONDUCTOR DEVICES

Non-Final OA §102§103
Filed
Nov 02, 2023
Examiner
FERNANDES, ERROL V
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
2y 3m
To Grant
96%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allow Rate
667 granted / 786 resolved
+16.9% vs TC avg
Moderate +12% lift
Without
With
+11.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
28 currently pending
Career history
814
Total Applications
across all art units

Statute-Specific Performance

§103
58.7%
+18.7% vs TC avg
§102
36.7%
-3.3% vs TC avg
§112
4.0%
-36.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 786 resolved cases

Office Action

§102 §103
DETAILED ACTION Election/Restrictions Applicant’s election without traverse of Species I, claims 1, 4, 5, 7-12 and 14-20, in the reply filed on 02/20/2026 is acknowledged. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. US 2022/0336330 A1. Regarding claim` 12, Kim discloses: A semiconductor device (Figs. 2 and 5C) comprising: a substrate (101/102) that has first and second surfaces opposite to each other in a first direction, the substrate comprising a buried pattern trench (portion of 101/102 filled by 255) that extends in the first direction from the second surface toward the first surface of the substrate and has a bottom surface including first and second concave areas (Fig. 5C; concave regions shown on 255 at either side of upper portion); a fin-type pattern (105) that protrudes in the first direction from the first surface of the substrate and extends in a second direction (see 105 in Fig. 2); a source/drain pattern (110) that is on the fin-type pattern and is electrically connected to the fin-type pattern; a source/drain contact (185/180A) that is on the source/drain pattern and is electrically connected to the source/drain pattern; a contact connection via (180B/120) that extends in the first direction and is electrically connected to the source/drain contact; first buried insulating liners (251) that extend along sidewalls and along the first and second concave areas of the buried pattern trench; and a buried conductive pattern (255) that is on the first buried insulating liners, is in the buried pattern trench, and is in contact with the contact connection via. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 14, 15 and 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. US 2022/0336330 A1 in view of Cho et al. US 2022/0399251 A1. Regarding claims 14, 15 and 17, Kim does not disclose: (claim 14) wherein the contact connection via includes upper and lower portions, wherein the upper portion of the contact connection via protrudes in the first direction beyond an upper surface of the source/drain contact and is in contact with the upper surface of the source/drain contact, and wherein the lower portion of the contact connection via is between the upper portion of the contact connection via and the buried conductive pattern; (claim 15) further comprising a front wiring via that is on the first surface of the substrate and is in contact with an upper surface of the source/drain contact, wherein the contact connection via includes upper and lower portions, wherein the upper portion of the contact connection via protrudes in the first direction beyond the upper surface of the source/drain contact and is in contact with the front wiring via, and wherein the lower portion of the contact connection via is between the upper portion of the contact connection via and the buried conductive pattern; and (claim 17) further comprising a front wiring via that is on the first surface of the substrate and is in contact with an upper surface of the source/drain contact and an upper surface of the contact connection via. Cho discloses a publication from a similar field of endeavor in which: (claim 14) wherein the contact connection via (79) includes upper and lower portions, wherein the upper portion of the contact connection via protrudes in the first direction beyond an upper surface of the source/drain contact (39) and is in contact with the upper surface of the source/drain contact (thru 45), and wherein the lower portion of the contact connection via is between the upper portion of the contact connection via and the buried conductive pattern (81) (see Fig. 3A); (claim 15) further comprising a front wiring via (45) that is on the first surface of the substrate and is in contact with an upper surface of the source/drain contact (39), wherein the contact connection via includes upper and lower portions, wherein the upper portion of the contact connection via protrudes in the first direction beyond the upper surface of the source/drain contact and is in contact with the front wiring via (thru 45), and wherein the lower portion of the contact connection via is between the upper portion of the contact connection via and the buried conductive pattern (81) (see Fig. 3A); and (claim 17) further comprising a front wiring via (45) that is on the first surface of the substrate and is in contact with an upper surface of the source/drain contact (39) and an upper surface of the contact connection via (connected to 79 thru 45) (see Fig. 3A). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to employ the alternative connection taught by Cho including an extended contact connection via electrically connected to the front wiring via on the source/drain contact to provide an intervening insulation layer reducing potential parasitic interference in the connection. Regarding claims 18-20, Kim discloses: A semiconductor device (Figs. 2 and 5C) comprising: a substrate (101/102) that has first and second surfaces opposite to each other in a first direction; a first fin-type pattern (105) that protrudes in the first direction from the first surface of the substrate and extends in a second direction; a second fin-type pattern (105) that protrudes in the first direction from the first surface of the substrate and is adjacent to the first fin-type pattern in a third direction; a first source/drain pattern (110) that is on the first fin-type pattern and is electrically connected to the first fin-type pattern; a second source/drain pattern (110) that is on the second fin-type pattern and is electrically connected to the second fin-type pattern; a first source/drain contact (185/180A) that is on the first source/drain pattern and is electrically connected to the first source/drain pattern; a second source/drain contact (185/180A) that is on the second source/drain pattern and is electrically connected to the second source/drain pattern; a contact connection via (180B/120) that is between the first and second source/drain contacts, extends in the first direction, and is electrically connected to the first source/drain contact; via insulating liners (182) that extend along sidewalls of the contact connection via and are in contact with the first and second source/drain contacts; a buried conductive pattern (255) that is in the substrate, is electrically connected to the contact connection via, and has first and second surfaces opposite to each other in the first direction, the first surface of the buried conductive pattern facing the first source/drain contact; and buried insulating liners (251) that extend along sidewalls and along the first surface of the buried conductive pattern, wherein the buried insulating liners include first and second curved portions on the first surface of the buried conductive pattern (Fig. 5C; concave regions shown on 255 at either side of upper portion with 251 having curved portions), wherein the contact connection via is between the first and second curved portions of the buried insulating liners (Fig. 5C; 180B/120 between concave regions shown on 255 at either side of upper portion with 251 having curved portions), and wherein outer surfaces of the first and second curved portions of the buried insulating liners that are in contact with the substrate have a convex shape (Fig. 5C; concave regions shown on 255 at either side of upper portion with 251 having curved portions). Kim does not disclose: wherein the contact connection via includes an upper portion that protrudes in the first direction beyond an upper surface of the first source/drain contact, and a lower portion that is between the upper portion of the contact connection via and the buried conductive pattern. Cho discloses a publication from a similar field of endeavor in which: wherein the contact connection via (79) includes an upper portion that protrudes in the first direction beyond an upper surface of the first source/drain contact (39), and a lower portion that is between the upper portion of the contact connection via and a buried conductive pattern (81) (see Fig. 3A). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to employ the alternative connection taught by Cho including an extended contact connection via electrically connected to the front wiring via on the source/drain contact to provide an intervening insulation layer reducing potential parasitic interference in the connection. (claim 19) Cho; connection via (79) in contact (thru 45) with the upper surface of the first source/drain contact (39) (Fig. 3A). (claim 20) Cho; a front wiring via (45) in contact with the upper surface of the first source/drain contact (39), wherein the upper portion of the contact connection via (79) is in contact with a sidewall of the front wiring via (at least at the corner of the sidewall thru wiring 45). Allowable Subject Matter Claims 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art fails to teach or clearly suggest the limitations of claim 16 stating “wherein the source/drain pattern includes a bottom surface electrically connected to the fin-type pattern, wherein a height from the bottom surface of the source/drain pattern to an upper surface of the source/drain contact is greater than a height from the bottom surface of the source/drain pattern to an upper surface of the contact connection via, and wherein the source/drain contact is in contact with the upper surface of the contact connection via”. In light of these limitations, the prior art fails to anticipate or make obvious the claimed invention. Claims 1, 4, 5, 7-11 are allowed. The following is an examiner’s statement of reasons for allowance: The prior art fails to teach or clearly suggest the limitations of claim 1 stating “wherein a thickness of a first portion of at least one of the first buried insulating liners that is on a respective one of the sidewalls of the buried conductive pattern is less than a thickness of a second portion of the at least one of the first buried insulating liners that is on the first surface of the buried conductive pattern”. In light of these limitations, the prior art fails to anticipate or make obvious the claimed invention. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERROL V FERNANDES whose telephone number is (571)270-7433. The examiner can normally be reached on 9-5:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERROL V FERNANDES/Primary Examiner, AU 2893
Read full office action

Prosecution Timeline

Nov 02, 2023
Application Filed
Mar 07, 2026
Non-Final Rejection — §102, §103
Apr 07, 2026
Applicant Interview (Telephonic)
Apr 09, 2026
Examiner Interview Summary

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
96%
With Interview (+11.6%)
2y 3m
Median Time to Grant
Low
PTA Risk
Based on 786 resolved cases by this examiner. Grant probability derived from career allow rate.

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