DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
The following office action is in response to the amendment and remarks filed on 6/10/26.
Applicant’s amendment to claims 1 and 15 is acknowledged.
Applicant’s cancellation of claims 16 is acknowledged.
Claims 1-15 and 17-20 are pending and subject to examination at this time.
Response to Arguments
Applicant's arguments with respect to claim 1 have been considered but are moot in view of the new ground(s) of rejection.
Allowable Subject Matter
Claims 15 and 17-20 is allowed.
Claims 2-4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhou et al., CN 114843305 A (see attached English machine translation).
Zhou anticipates:
1. An integrated circuit, comprising (see figs. 2-3):
a first electrode (100);
a second electrode (300); and
a body of a phase change material (201) coupled between the first electrode and the second electrode,
wherein the phase change material comprises SixSbyTez, where x, y, z represent respective atomic ratios for compositions Si, Sb, Te, (e.g. See Si10Ga30Sb50Te10 at page 13) and
wherein a bulk stoichiometry of the body of the phase change material comprises a Si atomic concentration within a range from about 7% to about 12%, wherein the phase change material is free of Germanium (Ge) (e.g. See Si10Ga30Sb50Te10 at page 13). See Zhou at English machine translation pages 8-10 and 13.
Claim(s) 1 and 11-13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chuang et al., US Publication No. 2012/0181499 A1.
Chuang anticipates:
1. An integrated circuit, comprising (see fig. 1):
a first electrode (111);
a second electrode (114); and
a body of a phase change material (115) coupled between the first electrode and the second electrode,
wherein the phase change material comprises SixSbyTez, where x, y, z represent respective atomic ratios for compositions Si, Sb, Te (see Table 1 at para. [0071] with 10.1% Si, 66.1% Sb and 9.2% Te), and
wherein a bulk stoichiometry of the body of the phase change material comprises a Si atomic concentration within a range from about 7% to about 12%, wherein the phase change material is free of Germanium (Ge) (see Table 1 at para. [0071] with 10.1% Si, 66.1% Sb and 9.2% Te). See Chuang at para. [0001] – [0084], figs. 1-18.
11. The integrated circuit of claim 1, wherein the phase change material has a crystallization temperature greater than 200° C (e.g. See temperature Tx of Si at 10.1% in fig. 10)
12. The integrated circuit of claim 1, wherein the body of a phase change material is configured to be applied with a set pulse having a duration of no more than 200 ns to change the phase change material from an amorphous phase to a crystalline phase, para. [0081] – [0082], also see para. [0030], [0067] – [0068].
13. The integrated circuit of claim 1, configured to be a memory element with a mushroom type structure, para. [0037].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chuang, as applied to claim 1 above, in view of Cheng[1] et al., US Patent No. 10,050,196 (of record).
Regarding claim 5:
Chuang teaches all the limitations of claim 1 above, but is silent regarding the thickness of the phase change material.
In an analogous art, Cheng[1] teaches:
wherein the body of the phase change material has a thickness in a range from 30 nm to 80 nm (e.g. 50 to 100 nm), col 4, ln 35–45.
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). “[A] prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003). See MPEP § 2144.05, Obviousness of Ranges
Referring to MPEP § 2144.05, “…the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results over the prior art range.” (See also MPEP § 716.02 for a discussion of criticality and unexpected results.)
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Chuang with the teachings of Cheng[1] because a thickness of 50 to 100 nm is an art recognized thickness suitable in a phase change memory device. See MPEP § 2144.07, Art Recognized Suitability for an Intended Purpose.
Claim(s) 6 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chuang, as applied to claim 1 above, in view of Li et al., US Publication No. 2021/0143325 A1.
Regarding claims 6-7:
Chuang teaches all the limitations of claim 1 above, but does not expressly teach:
wherein a reset drift coefficient of the integrated circuit at a room temperature is no more than 0.04;
wherein a reset drift coefficient of the integrated circuit at an elevated temperature is no more than 0.04.
In an analogous art, Li teaches “In general, PCM cells containing GST as the PCM material exhibit a positive reset state resistance drift coefficient (i.e., at the reset state the resistance increases over time). Reset state resistance drift can be especially problematic when the PCM cell is used as analog memory in neuromorphic computing. There is thus a need to provide a PCM cell in which the reset state resistance drift can be reduced.” See Li at para. [0004]
Li further teaches a reset drift coefficient less than 0.05, which overlaps the claimed range. See Li at para. [0025].
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). “[A] prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003). See MPEP § 2144.05, Obviousness of Ranges
Referring to MPEP § 2144.05, “…the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results over the prior art range.” (See also MPEP § 716.02 for a discussion of criticality and unexpected results.)
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Chuang with the teachings of Li to form “wherein a reset drift coefficient of the integrated circuit at a room temperature is no more than 0.04; wherein a reset drift coefficient of the integrated circuit at an elevated temperature is no more than 0.04” because Li teaches the reset drift coefficient needs to be reduced. See Li at para. [0004].
Claim(s) 8-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chuang, as applied to claim 1 above, in view of Cheng[3], US Publication No. 2020/0219933 A1 (of record).
Regarding claims 8-9:
Chuang teaches all the limitations of claim 1 above, but does not expressly teach:
wherein a change of a conductance of the integrated circuit at an elevated temperature is no more than 10% over 1 hour;
wherein a change of a conductance of the integrated circuit at an elevated temperature is no more than 10% over 1 day.
In an analogous art, Cheng[3] teaches:
“For some applications such as, for example, analog computing or neuromorphic applications, it is desired to have the electrical conductance of a PCM cell changing gradually (or at least multiple bits) instead of abruptly.”, para. [0003].
“In some embodiments, the PCM cells of the present application can be used in analog (or neuromorphic) computing to represent the weights in machine learning models. The gradual change of electrical conductance in both the SET and RESET operations is beneficial in those applications.”, para. [0052].
It would have been obvious to one of ordinary skill in the art to form “wherein a change of a conductance of the integrated circuit at an elevated temperature is no more than 10% over 1 hour; wherein a change of a conductance of the integrated circuit at an elevated temperature is no more than 10% over 1 day” because Cheng[3] teaches a gradual change in conductance enables change to occur in multiple bits when applied to machine learning.
Regarding claim 10:
Chuang teaches all the limitations of claim 1 above and further teaches:
10. The integrated circuit of claim 1, wherein the body of the phase change material is programmable to a plurality of resistance states including a full reset state and a full set state, para. [0067] – [0068], para. [0081] – [0082].
Chuang does not expressly teach:
wherein a change of a conductance of each of the plurality of resistance states is no more than 10% over 1 day.
Cheng[3] teaches this limitation as applied to claim 9 above.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Chuang with the teachings of Cheng[3] because the gradual change of electrical conductance in both the SET and RESET operations is beneficial in machine learning applications. See Cheng[3] at para. [0052].
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chuang as applied to claim 1 above, in view of Brew et al., US Publication No. 2022/0209105 A1 (of record) and Cheng[3], US Publication No. 2020/0219933 A1 (of record).
Regarding claim 14:
Chuang teaches all the limitations of claim 1 above, and further teaches:
14. A phase change memory device, comprising a plurality of memory cells, wherein at least one of the plurality of memory cells comprises the integrated circuit of claim 1, figs. 5-6.
Chaung does not expressly teach:
wherein the phase change memory device is configured to perform an inference mode of an analog artificial intelligence (AI) model, and wherein, in the inference mode, memory elements of the plurality of memory cells are programmed to have a plurality of resistance states corresponding to respective weights of the plurality of memory cells, the plurality of resistance states corresponding to non-overlapping ranges of resistance values.
In an analogous art, Brew teaches:
wherein the phase change memory device is configured to perform an inference mode of an analog artificial intelligence (AI) model, and wherein, in the inference mode,… , para. [0002].
In an analogous art, Cheng[3] teaches:
(see fig. 10A) wherein the phase change memory device is configured to perform…[in] an analog artificial intelligence (AI) model,…memory elements of the plurality of memory cells are programmed to have a plurality of resistance states (e.g. SET, RESET) corresponding to respective weights of the plurality of memory cells, the plurality of resistance states (e.g. SET, RESET) corresponding to non-overlapping ranges of resistance values (e.g. resistances values on y-axis; see para. [0001] disclosing electrical conductance in fig. 10A is the inverse of electrical resistance). See Cheng[3] at para. [0052].
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Chuang with the teachings of Brew because phase change memory (PCM) can be utilized for both training and inference in artificial intelligence. “The phase change memory structures can include phase change memristive devices with tunable conductivities from device to device and overall high device resistance with high retention to minimize energy consumption. See Brew at para. [0002].
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Chuang] with the teachings of Cheng[3] because “In some embodiments, the PCM cells of the present application can be used in analog (or neuromorphic) computing to represent the weights in machine learning models. The gradual change of electrical conductance in both the SET and RESET operations is beneficial in those applications.” See Cheng[3] at para. [0052].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michele Fan whose telephone number is 571-270-7401. The examiner can normally be reached on M-F from 7:30 am to 4 pm.
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/Michele Fan/
Primary Examiner, Art Unit 2818
19 August 2026
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