DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 and 8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 20100084175 (Suzuki et al).
Concerning claim 1, Suzuki discloses a packaging substrate (10) comprising (Figs. 5-12): a cavity region (90) in which an element (101) is accommodated ([0059] and Fig. 8); and a core substrate (11) in which the cavity region is disposed (Fig. 7), wherein the cavity region comprises an accommodation portion that is a space formed by recessing a portion of the core substrate (Figs. 7 and 8), a side surface that is formed in a thickness direction of the core substrate and forms an outer periphery of the accommodation portion (Figs. 7 and 8, note that the core substrate has a thickness that surrounds the cavity), and an elastic layer (173/92) disposed in contact with the side surface of the cavity region (Figs. 10 and 11 and [0065]-[0067]), wherein an elastic modulus of the elastic layer is 2 GPa to 15 GPa ([0054] and [0077]).
Continuing to claim 2, Suzuki discloses wherein a thermal expansion coefficient value of the elastic layer is 30 ppm/°C to 70 ppm/°C ([0053] and [0075]).
Considering claim 3, Suzuki disclose comprising a redistribution layer (31) disposed on the core substrate (Fig. 12), wherein the redistribution layer comprises an insulating layer (33 and 35) and an electrically conductive layer (42 and 47) disposed in the insulating layer (Fig. 12 and [0069]-[0070]), and a difference value between a thermal expansion coefficient value of the insulating layer and a thermal expansion coefficient value of the elastic layer is less than or equal to 60 ppm/°C ([0076], it is noted that Suzuki discloses a CTE of the elastic layer 92 is 57 ppm/°C and the CTE of the insulating layer 33/35 is 39 ppm/°C. Therefore the examiner the CTE difference between thermal expansion coefficient value of the insulating layer and a thermal expansion coefficient value of the elastic layer is (57-39) 18 ppm/°C which is less than the claimed 60 ppm/°C and therefore this limitation is met).
Regarding claim 8, Suzuki disclose comprising a buffer layer (34) disposed under the core substrate (Fig. 12), wherein a thermal expansion coefficient of the buffer layer is 10 ppm/°C to 50 ppm/°C ([0076]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20100084175 (Suzuki et al).
Referring to claim 4, Suzuki discloses having a core substrate (11) with a specified CTE ([0019] and [0056]).
Suzuki does not disclose wherein a thermal expansion coefficient of the core substrate is from 5 ppm/°C to 20 ppm/°C. However, Suzuki discloses that the material of the core substrate is not particularly limited. Preferably, the core substrate is formed using a high molecular weight material as its major body. Specific examples of the high molecular weight material useful for forming the core substrate include EP resin (epoxy resin), PI resin (polyimide resin), BT resin (bismaleimide triazine resin), PPE resin (polyphenylene ether resin), and the like ([0019]), but ultimately chooses a material that has a CTE of 27 ppm/°C ([0056]) which is close to the claimed range. A prima facie case of obviousness exists where the claimed ranges or amounts do not overlap with the prior art but are merely close. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40°C and 80°C and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100°C and an acid concentration of 10%). See MPEP 2144.05 I. Therefore it would have been obvious to one of ordinary skill in the art to use a material with a CTE within the claimed range absent such range is significant.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20100084175 (Suzuki et al) as applied to claim 1 above, and further in view of US 20150014034 (Hwang et al) and US 10756054 (Huang).
Pertaining to claim 5, Suzuki discloses forming the cavity in the core substrate (Fig. 7).
Suzuki does not disclose wherein an angle of the side surface of the cavity region with respect to a lower surface of the core substrate is greater than or equal to 60° and less than 90°, and a minimum value of a thickness of the elastic layer in an in-plane direction of the core substrate is 2 µm to 45 µm. However, Hwang discloses a package configuration (Fig. 6) in which the cavity (200) walls formed in a core substrate (100) are tapered at range of 52.4° to 71.6° ([0060]) and that the cavity structure is capable of reducing factors of a defect due to sequential lamination which is essential to embed an electronic device and the number of processes ([0011]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to form the walls of the cavity at 60° and less than 90° (an internal value of this range disclosed by Hwang) in order to reduce defects in the packaging device.
Also Huang discloses a package configuration (Figs. 4B and 4C) in which a cavity (11C) is formed in a core substrate (11) and an elastic layer (16) is formed in contact with the side surfaces of the cavity with a thickness of this elastic layer in an in-plane direction of the core substrate greater than 500 µm (note that the minimum value of the thickness of elastic layer is required to be only 2 µm to 45 µm and these values are well above that) and that such thickness allows for the elastic material to cure leaving substantially a smooth upper surface which is ideal for subsequent lamination operations (col. 3 lines 63-67 and col. 4 lines 1-26). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to form the elastic material at the side surface of the cavity at the disclosed thickness of Huang in order to provide a smooth upper surface and facilitate ideal conditions form subsequent lamination.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20100084175 (Suzuki et al) as applied to claim 1 above, and further in view of US 20110308848 (Ito et al).
As to claim 6, Suzuki disclose forming the cavity (Fig. 7).
Suzuki does not disclose an Ra value (an arithmetic average roughness) of the side surface of the cavity region is 1 µm to 50 µm. However, Ito discloses a package configuration (Figs. 6a-6c) that includes a composite body comprising resin layer (1) wherein the resin layer has via hole (4) and the surface of the resin layer of the inside of the via hole has an arithmetic average roughness (Ra) of 0.05 µm or more and 0.45 µm ([0066] and [0068]). Ito notes that such configuration can effectively exert the effects of connection failure between layers ([0068]). A prima facie case of obviousness exists where the claimed ranges or amounts do not overlap with the prior art but are merely close. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40°C and 80°C and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100°C and an acid concentration of 10%). See MPEP 2144.05 I. Therefore it would have been obvious to one of ordinary skill in the art to modify the roughness of the sidewalls of the cavity such that its Ra value is within the claimed range in order to reduce connection failure between the substrate and absent such range is significant.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20100084175 (Suzuki et al) as applied to claim 1 above, and further in view of US 20240421116 (Cunningham et al).
Concerning claim 7, Suzuki disclose forming the elastic layer.
Suzuki does not disclose wherein a surface energy of the elastic layer is 15 dyne/cm to 35 dyne/cm. However, Cunningham discloses a configuration in which an epoxy barrier (60) comprises a polymer having a surface energy less than that of the epoxy resin (40) (similar to the elastic layer and the core substrate materials). Since the surface tension of epoxy resins is generally low (20-30 dyne/cm), it is important that the surface energy of the epoxy barrier be below this range in order to properly repel the epoxy resin and keep it from overflowing the barrier. Typically, the epoxy barriers will have surface energies below 20 dyne/cm, and often less than 15 dyne/cm ([0030]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use a polymer with the claimed surface energies of Cunningham in order to allow for containment of the epoxy layers in their respective areas.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 7656015 (Wong et al) in view of US 20170096530 (Yun et al).
Continuing to claim 9, Wong discloses a packaging substrate comprising (Figs. 2A -2F): a cavity region (201 +202) in which an element (22 and 22’) is accommodated; and a core substrate (20) in which the cavity region is disposed (Fig. 2B), wherein the cavity region comprises an accommodation portion that is a space formed by recessing a portion of the core substrate (Fig. 2A), two or more elements accommodated in the accommodation portion (Fig. 2B), and an elastic layer (21C) disposed adjacent to the side surface (Fig. 2B).
Wong does not disclose wherein an elastic modulus of the elastic layer is 2 GPa to 15 GPa. Yun discloses a polymer that has a modulus of 4 GPa or leas and a coefficient of thermal expansion of 30 to 200 ppm and that prevents warpage after high-temperature treatments ([0039]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the polymer film of Yun as the elastic layer in the invention of Wong because it is a suitable elastic material for use as the elastic film that provides the benefit of preventing warpage after high temperature processes.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20100084175 (Suzuki et al) as applied to claim 1 above, and further in view of US 20200066670 (Dominguez et al).
Considering claim 10, Suzuki discloses a semiconductor package comprising: the packaging substrate according to claim 1 (Fig. 13).
Suzuki does not explicitly disclose a main board electrically connected to the packaging substrate. Suzuki discloses that the package substrate of Fig. 13 has external connections that are used to connect the package substrate to an electronic device. Dominguez discloses a package substrate (106) may be mounted on a circuit board (108) with the package substrate containing a ball grid array (BGA) component having several solder balls arranged in a ball field with each solder ball being mounted and attached to a corresponding contact pad of circuit board. Circuit board may be a motherboard or another printed circuit board of a computer system or device, e.g., a flash memory stick and the solder ball and contact pad attachments may provide a physical and electrical interface between the dies of semiconductor package ([0015]). The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See MPEP 2144.07. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the circuit board of Dominguez as the additional electronic device connected to Suzuki because it is a suitable electronic device for connection to a package such as Suzuki.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-8 and 10 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
In response to applicant's argument that US 20170096530 (Yun et al) is nonanalogous art, it has been held that a prior art reference must either be in the field of the inventor’s endeavor or, if not, then be reasonably pertinent to the particular problem with which the inventor was concerned, in order to be relied upon as a basis for rejection of the claimed invention. See In re Oetiker, 977 F.2d 1443, 24 USPQ2d 1443 (Fed. Cir. 1992). In this case, Chia discloses a buffer layer 24 of that is disclosed as being used as a material to fix the semiconductor chip to the substrate (col. 4 lines 25-28), which is the same function of an adhesive layer (similar to the adhesive layer of Wong). Chia recognizes the need for the use of a polymer that has a low coefficient of thermal expansion (CTE and a low Young’s Modulus to prevent delamination from occurring. Yun disclose a material (polymer film) that meets these characteristics and is capable of performing the desired function of preventing delamination. Therefore the examiner believes that the references are reasonably pertinent to a known particular problem of delamination (which is a problem that can be associated with adhesive materials) and the rejection stands.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VALERIE N NEWTON whose telephone number is (571)270-5015. The examiner can normally be reached M-F 8-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD DICKE can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VALERIE N NEWTON/Examiner, Art Unit 2897 06/12/26
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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