Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
New claim 9 has been added. Currently claims 1-9 are pending.
DETAILED ACTION
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-9 are rejected under 35 U.S.C. 103 as being unpatentable over Yamaguchi et al. (Pub. No. US 2012/0106220 A1, herein Yamaguchi) in view Katoh (Pub. No. US 2022/0020730 A1).
Regarding claim 1, Yamaguchi discloses a semiconductor device comprising: a plurality of semiconductor elements 22 each having a control electrode configured to control a main current (Yamaguchi: paragraphs [0069], [0075]-[0076]); a metal electrode through which the main current of the plurality of semiconductor elements flows (Yamaguchi: paragraphs [0047]-[0050]); and a control wire connecting each of the control electrodes of the plurality of semiconductor elements in series (Yamaguchi; Figs. 1-20B and paragraphs [0118]-[0124]), and interlinked with a magnetic field generated when the main current flows through the metal electrode (Yamaguchi; Figs. 1-20B and paragraph [0173]).
Yamaguchi does not specifically show a control wire connecting each of the gate electrodes of the plurality of semiconductor elements in series.
However, in the same field of endeavor, Katoh teaches a semiconductor device comprising: a plurality of semiconductor elements 20 (Katoh: paragraphs [0064]-[0065]) each having a gate electrode (gate electrode of transistors 111, 112, etc.) configured to control a main current (Katoh: paragraph [0057]); and a control wire 7-8 connecting each of the gate electrodes of the plurality of semiconductor elements in series, and interlinked with a magnetic field generated (Katoh: paragraph [0123]) when the main current flows through the metal electrode to reduce the effect of the inductance, which as a result reduces the surge voltage (Katoh: paragraph [0062] and Fig. 1).
Therefore, given the teachings of Katoh, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Yamaguchi in view of Katoh by employing the control wire.
Regarding claim 2, Yamaguchi in view of Katoh teaches the semiconductor device according to claim 1, wherein the control wire is provided in the vicinity of an end portion of the metal electrode when viewed from a direction in which the main current flows in the metal electrode (Yamaguchi; Figs. 2, 5-12, 18-19 and paragraphs [0041]-[0046]).
Regarding claims 3 and 6, Yamaguchi in view of Katoh teaches the semiconductor device according to claim 1, wherein based on induced electromotive forces that are to be cumulatively applied to the control electrodes of the semiconductor elements by the magnetic field, distances between portions of the control wire corresponding to the induced electromotive forces and the metal electrode are set (Yamaguchi; Figs. 14A-14C and paragraphs [0099]-[0100], [0121]).
Regarding claims 4 and 7, Yamaguchi in view of Katoh teaches the semiconductor device according to claim 1, wherein based on the induced electromotive forces that are to be cumulatively applied to the control electrodes of the semiconductor elements by the magnetic field, angles between the extending direction of portions of the control wire corresponding to the induced electromotive forces and a direction of the main current in the metal electrode in plan view are set (Yamaguchi; Figs. 2, 5-12, 18-19 and paragraphs [0099]-[0100], [0121]).
Regarding claims 5 and 8, Yamaguchi in view of Katoh teaches the semiconductor device according to claim 1, further comprising an insulating layer provided on a surface of the metal electrode on the control wire side (Yamaguchi; 2, 5-12, 18-19 and paragraphs [0046], [0057]).
Regarding claim 9, Yamaguchi in view of Katoh teaches the semiconductor device according to claim 1, further comprising another metal electrode (Katoh: paragraph [0058]) through which the main current of the plurality of semiconductor elements flows, wherein the control wire connects each of the gate electrodes of the plurality of semiconductor elements to each other in series (Katoh: paragraph [0062] and Fig. 1), and interlinked with the magnetic field generated when the main current flows through the metal electrode and the another metal electrode (Yamaguchi; Figs. 2, 5-12, 18-19 and paragraphs [0041]-[0046] and Katoh: paragraph [0123]).
Claim 1 is also rejected under 35 U.S.C. 103 as being unpatentable over Waltrich et al. (Pub. No. US 2023/0387762 A1, herein Waltrich) in view Katoh (Pub. No. US 2022/0020730 A1).
Regarding claim 1, Waltrich discloses a semiconductor device comprising: a plurality of semiconductor elements each having a control electrode configured to control a main current (Waltrich: Figs. 2A-8B and paragraphs [0021], [0025], [0133]-[0134]); a metal electrode through which the main current of the plurality of semiconductor elements flows (Waltrich: Figs. 2A-8B and paragraphs [0010], [0133]-[0134]); and a control wire connecting each of the control electrodes of the plurality of semiconductor elements in series (Waltrich: Figs. 2A-8B and paragraphs [0032], [0087], [0133]-[0136]), and interlinked with a magnetic field generated when the main current flows through the metal electrode (Waltrich: Figs. 2A-8B and paragraphs [0221], [0229], [0324]).
Waltrich does not specifically show a control wire connecting each of the gate electrodes of the plurality of semiconductor elements in series.
However, in the same field of endeavor, Katoh teaches a semiconductor device comprising: a plurality of semiconductor elements 20 (Katoh: paragraphs [0064]-[0065]) each having a gate electrode (gate electrode of transistors 111, 112, etc.) configured to control a main current (Katoh: paragraph [0057]); and a control wire 7-8 connecting each of the gate electrodes of the plurality of semiconductor elements in series, and interlinked with a magnetic field generated (Katoh: paragraph [0123]) when the main current flows through the metal electrode to reduce the effect of the inductance, which as a result reduces the surge voltage (Katoh: paragraph [0062] and Fig. 1).
Therefore, given the teachings of Katoh, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Yamaguchi in view of Katoh by employing the control wire.
Response to Arguments
Applicant’s arguments with respect to claims 1-9 have been fully considered, but are found to be moot in view of the new grounds of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MALIHEH MALEK whose telephone number is (571)270-1874. The examiner can normally be reached M/T/W/R/F, 8:30-5.
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July 10, 2026
/MALIHEH MALEK/Primary Examiner, Art Unit 2813
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