DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 1 and 13, the limitation “first and second active patterns,” in combination with “each of the first bit line structure and the second bit line structure including: a first bit line extending in the first direction on the first active pattern; a second bit line extending in the first direction on the second active pattern,” is unclear as to how many first active patterns and how many second active patterns are required. Specifically, “first and second active patterns,” would appear to require only a first active pattern and a second active pattern, however each bit line structure having an associated first active pattern and an associated second active pattern would appear to require at least two first active patterns and two second active patterns.
Regarding claim 1, the limitation “the first and second patterns,” is unclear as to how it is related to “first and second active patterns.”
Regarding claims 4 and 16, the limitations “the bit line connector of the first and second bit line structures,” and “the bit line connector,” are unclear as to how the recitation of a single bit line connector is related to the previous recitation of a bit line connector of the first bit line structure and a bit line connect of the second bit line structure.
Regarding claim 4, the limitation “the first and second bit lines,” is unclear as to which first and second bit lines the limitation refers.
Regarding claim 5, the limitation “the outer spacer,” is unclear as to how it is related to the previously recited “first outer spacer” and “second outer spacer.”
Regarding claim 9, the limitation “a pitch of the first and second bit lines in the second direction is less than or equal to 130 nm” is unclear as to how the pitch can be close to 0 nm (i.e. a subset of pitches in the lower end of the recited range, as that would be understood to require at least a partial overlap of the first and second bit lines.
Regarding claim 19, the limitation “first and second active patterns,” in combination with “each of the first bit line structure and the second bit line structure including: a first bit line extending in the first direction on the first active pattern; a second bit line extending in the first direction on the second active pattern,” and “between the first (second) bit line of the first bit line structure and the first (second) active pattern,” is unclear as to how many first active patterns and how many second active patterns are required. Specifically, “first and second active patterns,” would appear to require only a first active pattern and a second active pattern, however each bit line structure having an associated first active pattern and an associated second active pattern would appear to require at least two first active patterns and two second active patterns.
Regarding claim 19, the limitation “a storage node contact on an edge portion of the first and second active patterns, respectively” is unclear if a single storage node contact is required or is plural storage node contacts (i.e. one on an edge portion of the first active pattern and one on an edge portion of the second active pattern) are required.
Regarding claim 19, the limitation “one or more landing pads on the storage node contacts, respectively” is unclear as to how many landing pads are required on each storage node contact.
Regarding claim 19, the limitation “one or more data storage patterns on the landing pads, respectively” is unclear as to how many landing pads are required on each storage node contact. It is further unclear as to how “the landing pads” (plural) is related to the “one or more landing pads,” in the instance it is one (singular) landing pad.
Regarding claim 20, the limitation “a first dummy pattern, wherein the first and second inner spacers extend around the first dummy pattern,” is unclear as to the proper interpretation of “first dummy pattern.” Specifically, it would appear that a first “dummy pattern” is surrounded by the first inner spacer and a second “dummy pattern” is surrounded by the second inner spacer, as shown in applicant’s disclosure. It is therefore unclear as to the proper interpretation of “dummy pattern” and “extends around.”
Note the dependent claims necessarily inherit the indefiniteness of the claims on which they depend.
Claim Rejections - 35 USC § 102/103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-7, 9-11, and 13-18 is/are rejected under 35 U.S.C. 103 as obvious over Feng et al. (US 9985035; herein “Feng”) in view of Kang (US 20150255304; herein “Kang”).
Regarding claim 1, Feng discloses in Fig. 7A and related text a semiconductor device comprising:
a substrate including a cell block region (e.g. region of 102) and a peripheral region (e.g region of 106)
first and second active patterns (108, see col. 3 line 39-40) adjacent to each other in a second direction, the first and second patterns being on the cell block region;
a first bit line structure, the first bit line structure including:
a first bit line (e.g. 162b’, see col. 6 lines 29-60) extending in the first direction on the first active pattern;
a second bit line (e.g. 162c’) extending in the first direction on the second active pattern; and
a bit line connector (e.g. 164, see col. 6 lines 29-60) connecting the first bit line and the second bit line to each other and adjacent to the peripheral region;
a first inner spacer (166 on inner sidewalls of 162b’ and 162c’, see col. 6 lines 61-62) on an inner surface of the bit line connector of the first bit line structure;
a first outer spacer (166 on outer sidewalls of 162b’ and 162c’, see col. 6 lines 61-62) on an outer surface of the bit line connector of the first bit line structure; and
wherein the first inner spacer extends on the inner surface of the bit line connector of the first bit line structure and continuously extends onto inner surfaces of the first bit line of the first bit line structure and the second bit line of the first bit line structure (formed on 150 and 160 without further masking and patterning, see col. 6 line 61 through col. 7 line 18).
In the alternative, it would have been obvious to have the first inner spacer extends on the inner surface of the bit line connector of the first bit line structure and continuously extends onto inner surfaces of the first bit line of the first bit line structure and the second bit line of the first bit line structure in order to form a spacer layer with simplified processing by avoiding additional masking and patterning steps of the spacer layer.
Feng does not explicitly disclose
the substrate including the cell block region and the peripheral region adjacent to each other in a first direction;
a second bit line structure adjacent the first bit line structure in the second direction and having the same structure as the first bi line structure.
In the same field of endeavor, Kang teaches in Fig. 1-2 and related text a semiconductor device comprising
the substrate including the cell block region (e.g. at least one “cell”) and the peripheral region (e.g. PC and SL) adjacent to each other in a first direction (see Fig. 1);
wherein the substrate further includes first and second cells spaced apart in the first direction (see Figs. 1-2 and [0046]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Feng by having multiple cell block regions in order to provide plural cells prior to dicing or to provide plural cells with spacing for a peripheral circuit (see Kang [0046]). Furthermore, it would have been obvious to one having ordinary skill in the art at the time the invention was made to have a duplicated cell block structure, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. It has also been held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). See also MPEP 2144.04. The limitation “wherein the semiconductor device further includes: a third active pattern and a fourth active pattern adjacent to each other in the second direction on the second cell block region; a third bit line extending in the first direction on the third active pattern; and a fourth bit line extending in the first direction on the fourth active pattern, and wherein the third bit line is electrically insulated from the fourth bit line” is therefore taught by the combination of the plural cells being a substantial duplicate of the individual cell, as shown by Kang, and the cell having the structure with the bit lines extending in the first direction and electrically insulated from each other, as shown by Feng.
The combined device therefore shows a second bit line structure adjacent the first bit line structure in the second direction and having the same structure as the first bi line structure by the combination of a cell region having the first bit line structure as claimed, as shown by Feng, and the device having a repeated cell structure, as shown by Kang. Accordingly, the repeated cell structure would be understood to include a second bit line structure including the same features as shown by the first bit line structure.
Regarding claim 2, Feng further discloses wherein the bit line connector of the first bit line structure is between the first inner spacer and the first outer spacer (between spacer on inner and outer sidewalls of 162b’ and 162c’).
Regarding claim 3, the combined device shows wherein the peripheral region is a scribe lane region or a peripheral region (Kang: see Fig. 1).
Regarding claim 4, the combined device shows wherein the bit line connector of the first and second bit line structures is curved toward the peripheral region in a plan view as the bit line connector extends from the first and second bit lines towards the peripheral region (Feng: see Fig. 7A; Kang: see Fig. 1).
Regarding claim 5, the combined device shows wherein the first outer spacer is curved toward the peripheral region in a plan view as the outer spacer extends from the first and second bit lines of the first bit line structure towards the peripheral region (Feng: see Fig. 7A; Kang: see Fig. 1).
Regarding claim 6, the combined device shows wherein the first outer spacer extends around the outer surface of the bit line connector of the first bit line structure (Feng: see Fig. 7A).
Regarding claim 7, the combined device shows wherein the first outer spacer extends on the outer surface of the bit line connector of the first bit line structure and continuously extends onto outer surfaces of the first bit line and the second bit line of the first bit line structure (Feng: see Fig. 7A; Kang: see Fig. 1).
Regarding claims 9 and 10, Feng does not explicitly disclose
wherein a pitch of the first and second bit lines of the first bit line structure in the second direction is less than or equal to 130 nm;
wherein a width of the first bit line of the first bit line structure in the second direction is wider than 0 nm and is less than or equal to 14 nm.
One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized the pitch and the width of the bit lines to be result effective variables affecting the size of the device and electrical characteristics such as parasitic capacitance between lines and resistance of the lines. Thus, it would have been obvious to modify the device of Feng to have the pitch and width within the claimed ranges in order to achieve a desired balance between various characteristics, and since optimum or workable ranges of such variables are discoverable through routine experimentation. see MPEP 2144.05 II.B and 2143. Furthermore, it has also been held that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936, (Fed. Cir. 1990). Note that the law is replete with cases in which when the mere difference between the claimed invention and the prior art is some dimensional limitation or other variable within the claims, patentability cannot be found. The instant disclosure does not set forth evidence ascribing unexpected results due to the claimed dimensions. See Gardner v. TEC Systems, Inc., 725 F.2d 1338 (Fed. Cir. 1984), which held that the dimensional limitations failed to point out a feature which performed and operated any differently from the prior art.
Regarding claim 11, Feng further discloses wherein a width of the first bit line of the first bit line structure in the second direction is narrower than or is equal to a distance from one end of the first inner spacer to one end of the bit line connector of the first bit line structure (equal to, see Fig. 7A).
Regarding claim 12, the combined device shows
wherein the cell block region is a first cell block region, wherein the substrate further includes a second cell block region spaced apart from the first cell block region in the first direction,
wherein the semiconductor device further includes: a third active pattern and a fourth active pattern adjacent to each other in the second direction on the second cell block region;
a third bit line extending in the first direction on the third active pattern; and
a fourth bit line extending in the first direction on the fourth active pattern, and wherein the third bit line is electrically insulated from the fourth bit line (Kang: see Fig. 1).
Furthermore, it would have been obvious to one having ordinary skill in the art at the time the invention was made to have a duplicated cell block structure, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. It has also been held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). See also MPEP 2144.04. The limitation “wherein the semiconductor device further includes: a third active pattern and a fourth active pattern adjacent to each other in the second direction on the second cell block region; a third bit line extending in the first direction on the third active pattern; and a fourth bit line extending in the first direction on the fourth active pattern, and wherein the third bit line is electrically insulated from the fourth bit line” is therefore taught by the combination of the plural cells being a substantial duplicate of the individual cell, as shown by Kang, and the cell having the structure with the bit lines extending in the first direction and electrically insulated from each other, as shown by Feng.
Regarding claim 13, Feng in view of Kang teaches the invention in substantially the same manner and for substantially the same reasons as applied to claim 1 above. Feng further teaches peripheral circuitry on the peripheral region (see col. 4 lines 24-25 at least) and wherein the inner spacer is curved toward the peripheral region in a plan view (formed on 150 and 160 without further masking and patterning, see col. 6 line 61 through col. 7 line 18).
Regarding claims 14-17, Feng further teaches the claims in substantially the same manner and for substantially the same reasons as applied to claims 2-4 and 7 above.
Regarding claim 18, the combined device shows a bit line trench region (Feng: e.g. region between 162b’ and 162c’) formed in the substrate between the first bit line of the first bit line structure and the second bit line of the first bit line structure and defined by an inner surface of the first bit line of the first bit line structure, an inner surface of the second bit line of the first bit line structure, and the inner surface of the bit line connector of the first bit line structure, wherein the first inner spacer is on an inner surface of the bit line trench region.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Feng and Kang, as applied to claim 1 above, and in view of Kim et al. (US 20210296237; herein “Kim”).
Regarding claim 8, Feng does not explicitly disclose wherein the first inner spacer includes a plurality of sub-spacers sequentially stacked on the inner surface of the first bit line of the first bit line structure, and wherein the first outer spacer includes a plurality of sub-spacers sequentially stacked on an outer surface of the first bit line of the first bit line structure.
In the same field of endeavor, Kim teaches in Fig. 1B and related text a semiconductor device comprising an inner spacer and an outer spacer (SP, see [0058]), wherein the inner spacer includes a plurality of sub-spacers sequentially stacked on the inner surface of the first bit line, and wherein an outer spacer includes a plurality of sub-spacers sequentially stacked on an outer surface of the first bit line (321/AG/325, see [0058]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Feng by having the inner spacer includes a plurality of sub-spacers sequentially stacked on the inner surface of the first bit line, and wherein an outer spacer includes a plurality of sub-spacers sequentially stacked on an outer surface of the first bit line, as taught by Kim, in order to reduce parasitic capacitance (see Kim [0058]).
Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Feng in view of Kang and Kim.
Regarding claim 19, Feng in view of Kang teaches the invention in substantially the same manner and for substantially the same reasons as applied to claim 1 above, and further teaches
bit line node contacts (126, see col. 4 lines 17-19) between the first bit line and the first active pattern and between the second bit line and the second active pattern;
storage node contacts (170, see col. 7 lines 27-32) on edge portions of the first and second active patterns, respectively;
wherein the inner spacer extends on the inner surface of the bit line connector and continuously extends onto inner surfaces of the first bit line and the second bit line (formed on 150 and 160 without further masking and patterning, see col. 6 line 61 through col. 7 line 18).
Feng does not explicitly disclose
landing pads on the storage node contacts, respectively; and
data storage patterns on the landing pads, respectively.
In the same field of endeavor, Kim teaches in Fig. 1B and related text a semiconductor device comprising
bit line node contacts (DC, see [0052]) between the first bit line and the first active pattern and between the second bit line and the second active pattern (between BL and 312a, see [0046] and [0050]);
storage node contacts (BC, see [0057]) on edge portions of the first and second active patterns (312a, see [0046]), respectively;
landing pads (LP, see [0058]) on the storage node contacts, respectively; and
data storage patterns (DSP, see [0063]) on the landing pads, respectively.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Feng by having bit line node contacts between the first bit line and the first active pattern and between the second bit line and the second active pattern; storage node contacts on edge portions of the first and second active patterns, respectively; landing pads on the storage node contacts, respectively; and data storage patterns on the landing pads, respectively, as taught by Kim, in order to achieve an appropriate contact structure for the memory device to allow for proper programming and operation.
Regarding claim 20, the combined device shows a first dummy pattern (Feng: e.g. insulating layer 168 filled between 162b’ and 162c’), wherein the first and second inner spacers extend around the first dummy pattern; and a second dummy pattern extending around the first and second outer spacers, wherein the second dummy pattern includes at least a portion comprising a material the same as the first dummy pattern.
Response to Arguments
Applicant's arguments filed 8/5/2026 have been fully considered but they are not persuasive.
Applicant argues (page 12) that Feng does not teach or suggest the inner and outer spacers as claimed because “Feng's spacer 166 is shown only in Fig. 8, which is a cross section…[of] a completely different embodiment than that in Fig. 7A,” and “is nowhere near any curve portion 164.” Applicant further argues that “there is no reason to believe any such spacers 166 would be present in the curve portion 164.”
In response, the examiner disagrees. Specifically, it is noted that “[a] reference may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art,” (see MPEP 2128.11.C). First, it is noted that Figs. 6A-B and 8 are the same embodiment. The cross-sectional view (Fig. 8) explicitly shows the spacer layer is added after the stage of processing shown in Fig. 6A-B. The spacer layer is omitted in the plan view of Fig. 6A because it is prior to the spacer layer being added. While Fig. 7A is a “modification of” the embodiment of Figs. 6A-B and 8, it is only modified in the plan view layout and presence of curved region 164. The cross-sectional view of Fig. 7A is synonymous to the cross-sectional view of Fig. 6A and one of ordinary skill in the art would readily recognize that the spacer layer of Fig. 8 is subsequently added in both the embodiment of Fig. 6A-B and the modification of Fig. 7A-B. While there is no drawing which explicitly shows the spacer layer being around the curved portion, one of ordinary skill would also readily recognize that, absent evidence to the contrary, the spacer layer would be added conformal to the entirety of 162b, 162c and 164.
Even assuming, for the sake of argument, that the this is not taught by the reference, the rejection above presents the alternative obviousness rationale that having the first inner spacer extend onto the inner surface of the bit line connector of the first bit line structure and continuously extends onto inner surfaces of the first bit line of the first bit line structure and the second bit line of the first bit line structure as claimed would be beneficial in that formation of the spacer layer would be simplified by avoiding additional masking and patterning steps of the spacer layer. Thus, even if Feng does not teach the spacer layer as claimed, it would have been an obvious modification to Feng.
Applicant’s remaining arguments have been considered but are moot in view of the new grounds of rejection presented above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20140131786 is cited for showing a spacer layer formed around a curved bit line connector (see Fig. 15A).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lauren R Bell whose telephone number is (571)272-7199. The examiner can normally be reached M-F 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LAUREN R BELL/ Primary Examiner, Art Unit 2896
