DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Group I, Species A in the reply filed on 4/8/2026 is acknowledged.
Claims 21-22 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 4/8/2026.
Claim Objections
Applicant is advised that should claim 5 be found allowable, claim 17 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 1, 13 and 19, the limitation “first and second active patterns adjacent to each other in a second direction that is different from the first direction on the cell block region” is unclear as to which of the preceding elements is required to be “on the cell block region.”
Regarding claims 3 and 15, the limitation “wherein the peripheral region is a scribe lane region or a peripheral region” is unclear, in the instance that of “the peripheral region is a…peripheral region,” as to how the latter recitation of “peripheral region” is related to the former recitation.
Regarding claims 4, 5, 13, 16, the limitation “the bit line (outer spacer/inner spacer) connector is curved toward the peripheral region in a plan view” is unclear as to what is required by “curved toward.” Specifically, “curved toward the peripheral region” would be understood as a deviation from an original path in a direction towards the peripheral region. However, as shown in applicant’s disclosure, it would seem the original path would be D1 and the curvature is towards D2, not towards the peripheral region 120. Accordingly, the proper scope and interpretation of the claim term cannot be ascertained.
Regarding claim 9, the limitation “a pitch of the first and second bit lines in the second direction is greater than 0 nm and is less than or equal to 130 nm” is unclear as to how the pitch can be close to 0 nm (i.e. a subset of pitches in the lower end of the recited range, as that would be understood to require at least a partial overlap of the first and second bit lines.
Regarding claim 18, the limitation “a bit line trench region,” is unclear as to what is required by the limitation. Specifically, a “trench region” would be understood to be require a region of a trench, however it is unclear as to what element contains a trench. It is further unclear because the specification does not make clear what trench the “bit line trench region” contains.
Regarding claim 19, the limitation “bit line node contacts between the first bit line and the first active pattern and between the second bit line and the second active pattern” is unclear as to the correspondence of elements. Specifically, it is unclear as to if plural bit line node contacts are required between the first bit line and the first active pattern and plural bit line node contacts are required between the second bit line and the second active pattern, or if a plural “bit line node contacts” could include a sing bit line node contact between the first bit line and the first active pattern and a single bit line node contact between the second bit line and the second active pattern.
Regarding claim 19, the limitation “storage node contacts on edge portions of the first and second active patterns, respectively” is unclear as to if plural storage node contacts are required on each edge portion.
Regarding claim 19, the limitation “landing pads on the storage node contacts, respectively,” is unclear as to if plural landing pads are required on each storage node contact.
Regarding claim 19, the limitation “data storage patterns on the landing pads, respectively,” is unclear as to if plural data storage patterns are required on each landing pad.
Regarding claim 20, the limitation “a first dummy pattern extended around by the inner spacer,” appears to contain a grammatical or typographical error rendering the meaning indefinite.
Note the dependent claims necessarily inherit the indefiniteness of the claims on which they depend.
Claim Rejections - 35 USC § 102/103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-7, 11, and 13-18 is/are rejected under 35 U.S.C. 102(a)(1) as anticipated by Feng et al. (US 9985035; herein “Feng”) or, in the alternative, under 35 U.S.C. 103 as obvious over Feng.
Regarding claim 1, Feng discloses in Fig. 7A and related text a semiconductor device comprising:
a substrate including a cell block region (e.g. region of 102) and a peripheral region (e.g region of 106) adjacent to each other in a first direction;
first and second active patterns (108, see col. 3 line 39-40) adjacent to each other in a second direction that is different from the first direction on the cell block region;
a first bit line (e.g. 162b’, see col. 6 lines 29-60) extending in the first direction on the first active pattern;
a second bit line (e.g. 162c’) extending in the first direction on the second active pattern;
a bit line connector (e.g. 164, see col. 6 lines 29-60) connecting the first bit line and the second bit line to each other and adjacent to the peripheral region;
an inner spacer (166 on inner sidewalls of 162b’ and 162c’, see col. 6 lines 61-62) on an inner surface of the bit line connector; and
an outer spacer (166 on outer sidewalls of 162b’ and 162c’, see col. 6 lines 61-62) on an outer surface of the bit line connector,
wherein the inner spacer extends on the inner surface of the bit line connector and continuously extends onto inner surfaces of the first bit line and the second bit line (formed on 150 and 160 without further masking and patterning, see col. 6 line 61 through col. 7 line 18).
In the alternative, it would have been obvious to have the inner spacer extends on the inner surface of the bit line connector and continuously extends onto inner surfaces of the first bit line and the second bit line in order to form a spacer layer with simplified processing by avoiding additional masking and patterning steps of the spacer layer.
Regarding claim 2, Feng further teaches wherein the bit line connector (164is between the inner spacer and the outer spacer (between spacer on inner and outer sidewalls of 162b’ and 162c’).
Regarding claim 3, Feng further teaches wherein the peripheral region is a scribe lane region or a peripheral region.
Regarding claim 4, Feng further teaches wherein the bit line connector (164) is curved toward the peripheral region in a plan view (see Fig. 7A).
Regarding claim 5, Feng further teaches wherein the outer spacer (166 along outer sidewall of 162b’ and 162c’) is curved toward the peripheral region in a plan view (see Fig. 7A).
Regarding claim 6, Feng further teaches wherein the outer spacer (166 along outer sidewall of 162b’ and 162c’) extends around the outer surface of the bit line connector.
Regarding claim 7, Feng further teaches wherein the outer spacer (166 along outer sidewall of 162b’ and 162c’) extends on the outer surface of the bit line connector and continuously extends onto outer surfaces of the first bit line and the second bit line (162b’ and 162c’).
Regarding claim 11, Feng further teaches wherein a width of the first bit line in the second direction is narrower than or is equal to a distance from one end of the inner spacer to one end of the bit line connector (equal to, see Fig. 7A).
Regarding claim 13, Feng teaches the invention in substantially the same manner and for substantially the same reasons as applied to claim 1 above, and further teaches wherein the inner spacer is curved toward the peripheral region in a plan view (formed on 150 and 160 without further masking and patterning, see col. 6 line 61 through col. 7 line 18).
In the alternative, it would have been obvious to have wherein the inner spacer is curved toward the peripheral region in a plan view in order to form a spacer layer with simplified processing by avoiding additional masking and patterning steps of the spacer layer.
Regarding claims 14-17, Feng further teaches the claims in substantially the same manner and for substantially the same reasons as applied to claims 2-4 and 7 above.
Regarding claim 18, Feng further discloses a bit line trench region (e.g. region between 16b’ and 162c’) defined by an inner surface of the first bit line, an inner surface of the second bit line, and the inner surface of the bit line connector, wherein the inner spacer is on an inner surface of the bit line trench region.
Claim Rejections - 35 USC § 103
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Feng, as applied to claim 1 above, and in view of Kim et al. (US 20210296237; herein “Kim”).
Regarding claim 8, Feng does not explicitly disclose wherein the inner spacer includes a plurality of sub-spacers sequentially stacked on the inner surface of the first bit line, and wherein an outer spacer includes a plurality of sub-spacers sequentially stacked on an outer surface of the first bit line.
In the same field of endeavor, Kim teaches in Fig. 1B and related text a semiconductor device comprising an inner spacer and an outer spacer (SP, see [0058]), wherein the inner spacer includes a plurality of sub-spacers sequentially stacked on the inner surface of the first bit line, and wherein an outer spacer includes a plurality of sub-spacers sequentially stacked on an outer surface of the first bit line (321/AG/325, see [0058]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Feng by having the inner spacer includes a plurality of sub-spacers sequentially stacked on the inner surface of the first bit line, and wherein an outer spacer includes a plurality of sub-spacers sequentially stacked on an outer surface of the first bit line, as taught by Kim, in order to reduce parasitic capacitance (see Kim [0058]).
Claim(s) 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Feng.
Regarding claims 9 and 10, Feng does not explicitly disclose
wherein a pitch of the first and second bit lines in the second direction is greater than 0 nm and is less than or equal to 130 nm;
wherein a width of the first bit line in the second direction is wider than 0 nm and is less than or equal to 14 nm.
One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized the pitch and the width of the bit lines to be result effective variables affecting the size of the device and electrical characteristics such as parasitic capacitance between lines and resistance of the lines. Thus, it would have been obvious to modify the device of Feng to have the pitch and width within the claimed ranges in order to achieve a desired balance between various characteristics, and since optimum or workable ranges of such variables are discoverable through routine experimentation. see MPEP 2144.05 II.B and 2143. Furthermore, it has also been held that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936, (Fed. Cir. 1990). Note that the law is replete with cases in which when the mere difference between the claimed invention and the prior art is some dimensional limitation or other variable within the claims, patentability cannot be found. The instant disclosure does not set forth evidence ascribing unexpected results due to the claimed dimensions. See Gardner v. TEC Systems, Inc., 725 F.2d 1338 (Fed. Cir. 1984), which held that the dimensional limitations failed to point out a feature which performed and operated any differently from the prior art.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Feng, as applied to claim 1 above, and in view of Kang (US 20150255304; herein “Kang”).
Regarding claim 12, Feng does not explicitly disclose
wherein the cell block region is a first cell block region,
wherein the substrate further includes a second cell block region of spaced apart from the first cell block region in the first direction,
wherein the semiconductor device further includes:
a third active pattern and a fourth active pattern adjacent to each other in the second direction on the second cell block region;
a third bit line extending in the first direction on the third active pattern; and
a fourth bit line extending in the first direction on the fourth active pattern, and
wherein the third bit line is electrically insulated from the fourth bit line.
In the same field of endeavor, Kang teaches in Fig. 1-2 and related text
wherein the cell block region is a first cell block region,
wherein the substrate further includes a second cell block region of spaced apart from the first cell block region in the first direction (see Figs. 1-2 and [0046]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Feng by having the cell block region is a first cell block region, wherein the substrate further includes a second cell block region of spaced apart from the first cell block region in the first direction in order to provide plural cells prior to dicing or to provide plural cells with spacing for a peripheral circuit (see Kang [0046]). Furthermore, it would have been obvious to one having ordinary skill in the art at the time the invention was made to have a duplicated cell block structure, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. It has also been held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). See also MPEP 2144.04. The limitation “wherein the semiconductor device further includes: a third active pattern and a fourth active pattern adjacent to each other in the second direction on the second cell block region; a third bit line extending in the first direction on the third active pattern; and a fourth bit line extending in the first direction on the fourth active pattern, and wherein the third bit line is electrically insulated from the fourth bit line” is therefore taught by the combination of the plural cells being a substantial duplicate of the individual cell, as shown by Kang, and the cell having the structure with the bit lines extending in the first direction and electrically insulated from each other, as shown by Feng.
Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Feng in view of Kim.
Regarding claim 19, Feng teaches the invention in substantially the same manner and for substantially the same reasons as applied to claim 1 above, and further teaches
bit line node contacts (126, see col. 4 lines 17-19) between the first bit line and the first active pattern and between the second bit line and the second active pattern;
storage node contacts (170, see col. 7 lines 27-32) on edge portions of the first and second active patterns, respectively;
wherein the inner spacer extends on the inner surface of the bit line connector and continuously extends onto inner surfaces of the first bit line and the second bit line (formed on 150 and 160 without further masking and patterning, see col. 6 line 61 through col. 7 line 18).
In the alternative, it would have been obvious to have wherein the inner spacer extends on the inner surface of the bit line connector and continuously extends onto inner surfaces of the first bit line and the second bit line in order to form a spacer layer with simplified processing by avoiding additional masking and patterning steps of the spacer layer.
Feng does not explicitly disclose
landing pads on the storage node contacts, respectively; and
data storage patterns on the landing pads, respectively.
In the same field of endeavor, Kim teaches in Fig. 1B and related text a semiconductor device comprising
bit line node contacts (DC, see [0052]) between the first bit line and the first active pattern and between the second bit line and the second active pattern (between BL and 312a, see [0046] and [0050]);
storage node contacts (BC, see [0057]) on edge portions of the first and second active patterns (312a, see [0046]), respectively;
landing pads (LP, see [0058]) on the storage node contacts, respectively; and
data storage patterns (DSP, see [0063]) on the landing pads, respectively.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Feng by having bit line node contacts between the first bit line and the first active pattern and between the second bit line and the second active pattern; storage node contacts on edge portions of the first and second active patterns, respectively; landing pads on the storage node contacts, respectively; and data storage patterns on the landing pads, respectively, as taught by Kim, in order to achieve an appropriate contact structure for the memory device to allow for proper programming and operation.
Regarding claim 20, the combined device shows
a first dummy pattern (e.g. insulating layer 168 filled between 162b’ and 162c’) extended around by the inner spacer; and
a second dummy pattern (e.g. 168 filled between 162b’ and 162a) extending around the outer spacer, wherein the second dummy pattern includes at least a portion comprising a material the same as the first dummy pattern.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20240179892 and US 20240357803 are cited for showing devices with curved bit line connectors.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lauren R Bell whose telephone number is (571)272-7199. The examiner can normally be reached M-F 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LAUREN R BELL/Primary Examiner, Art Unit 2896
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