DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-6 and 10-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yeong et al. (US 20210320111 A1) in further view of Liao et al. (US 20230142157 A1) and Hong et al. (US 20200403079 A1).
With regards to claim 1, Yeong et al. teaches a structure for a ferroelectric capacitive memory device, the structure comprising: a semiconductor layer [as seen in the attached Fig. 13, ¶0016, semiconductor layer is broad and the same function is seen to be done by the outlined portion in the attached Fig. 13];
a first electrode (semiconductor layer as seen in attached Fig. 13) including a first doped region (54) in the semiconductor layer and a second doped region (54) in the semiconductor layer [as seen in the attached Fig. 13, ¶0016, discusses heavily and lightly doped regions];
a first interconnection [74, as seen in the attached Fig. 13, ¶0021];
a ferroelectric layer on the semiconductor layer [132, as seen in the attached Fig. 13, ¶0047, with the definition of what is seen as the semiconductor layer, the layer 132 is on the semiconductor layer]; and
a second electrode including a first section and a second section on the ferroelectric layer [142 as seen in the attached Fig. 13, ¶0045, the second electrode can be divided up into two sections and each of those sections can be seen on the ferroelectric layer].
Yeong et al. doesn't teach the first interconnection configured to connect the first doped region to the second doped region, and the first section of the second electrode comprising a first material with a first work function, and the second section of the second electrode comprising a second material with a second work function that is greater than the first work function of the first material.
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Liao et al. teaches the use of interconnection structures and how an interconnection can be configured to connect the first doped region to the second doped region [¶0044, discusses a method that has interconnection structure to connect different layers and devices together].
It would have been obvious for a person with ordinary skill in the art before the effective filing date to use the teaching of Liao et al. in Yeong et al. and create an interconnection to connect doped regions as required by the claim, because the interconnects of Yeong et al. connect the electrodes to conductive features and Liao et al. teaches that the interconnects used to connect source and drain regions and gates stacks thus within the purview of an artisan to use in Yeong et al.
Yeong et al. in view of Liao et al. does not disclose the second electrode where the first section of the second electrode comprising a first material with a first work function, and the second section of the second electrode comprising a second material with a second work function that is greater than the first work function of the first material.
Hong et al. teaches a first and second electrode where the second electrode includes a first section (110a) and a second section (114), the first section of the second electrode comprising a first material with a first work function, and the second section of the second electrode comprising a second material with a second work function that is greater than the first work function of the first material [as seen in attached Fig. 6, ¶0073, discloses the two different materials have different work functions]. Hong et al. teaches a first section 110a having a lower work function than the second portion 114 as Hong discloses the impurity region 130 to be utilized as a source/drain region and is doped to be an n-type transistor which is known to have the source/drain regions have a higher work function than the metal electrodes. Since it is known that 130 and 114 would have similar work functions and 130 and 110a have different work functions, person with ordinary skill in the art would be able to come to the conclusion that the second portion 114 has a higher work function than the first portion 110a.
It would have been obvious for a person with ordinary skill in the art before the filing date of the invention to incorporate the teachings of Hong et al. in the combined device of Yeong et al. in view of Liao et al. as required by the claims because the structure would allow for a more stable and efficient memory device. Having a section with a different work function can help with reducing leakage from the electrode as taught by Hong et al.
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With regards to claim 2, Yeong et al. in further view of Liao et al. and Hong et al. teaches the structure of claim 1 and wherein the first section (110a, Hong et al.) of the second electrode directly contacts the second section (114, Hong et al.) of the second electrode [as seen in attached Fig. 6, ¶0073, Hong et al.].
With regards to claim 3, Yeong et al. in further view of Liao et al. and Hong et al. teaches the structure of claim 2 and wherein the first section (110a, Hong et al.) of the second electrode and the second section of the second electrode (114, Hong et al.) have a juxtaposed relationship [as seen in attached Fig. 6, ¶0073, Hong et al., they are seen to be right next to each other].
With regards to claim 4, Yeong et al. in further view of Liao et al. and Hong et al. teaches the structure of claim 1 and wherein the ferroelectric layer (132, Yeong et al.) is disposed fully between the first section of the second electrode (142, Yeong et al.) and the semiconductor layer (shown in attached Fig. 13, Yeong et al.), and the ferroelectric layer (132, Yeong et al.) is disposed fully between the second section of the second electrode (142, Yeong et al.) and the semiconductor layer (shown in attached Fig. 13, Yeong et al.) [¶¶0050-0052].
With regards to claim 5, Yeong et al. in further view of Liao et al. and Hong et al. teaches the structure of claim 4 and wherein the first section of the second electrode (142, Yeong et al.) directly contacts a first portion of the ferroelectric layer (132, Yeong et al.), and the second section of the second electrode directly contacts a second portion of the ferroelectric layer [142 as seen in the attached Fig. 13, ¶0045, Yeong et al.].
With regards to claim 6, Yeong et al. in further view of Liao et al. and Hong et al. teaches the structure of claim 5 and wherein the first section of the second electrode (110a) laterally adjoins the second section of the second electrode (114) [as seen in attached Fig. 6, ¶0073, Hong et al.].
With regards to claim 10, Yeong et al. in further view of Liao et al. and Hong et al. teaches the structure of claim 1 and wherein the second electrode includes a third section (C as seen in attached Fig. 6), the first section (B as seen in attached Fig. 6) is disposed laterally between the second section (A as seen in attached Fig. 6) and the third section (C as seen in attached Fig. 6), and the third section comprises the second material [¶0073, Hong et al.].
With regards to claim 11, Yeong et al. in further view of Liao et al. and Hong et al. teaches the structure of claim 10 and wherein the first section of the second electrode (B as seen in attached Fig. 6) is coextensive with the second section of the second electrode section (A as seen in attached Fig. 6), and the first section of the second electrode (B as seen in attached Fig. 6) is coextensive with the third section of the second electrode (C as seen in attached Fig. 6) [¶0073, Hong et al.].
With regards to claim 12, Yeong et al. in further view of Liao et al. and Hong et al. teaches the structure of claim 1 and wherein the second electrode includes a third section (C as seen in attached Fig. 6), the second section (B as seen in attached Fig. 6) is disposed laterally between the first section (A as seen in attached Fig. 6) and the third section, and the third section comprises the first material [¶0073, Hong et al.].
With regards to claim 13, Yeong et al. in further view of Liao et al. and Hong et al. teaches the structure of claim 12 and wherein the second section of the second electrode is coextensive (B as seen in attached Fig. 6) with the first section of the second electrode (A as seen in attached Fig. 6), and the second section of the second electrode is coextensive with the third section of the second electrode (C as seen in attached Fig. 6) [¶0073, Hong et al.].
With regards to claim 14, Yeong et al. in further view of Liao et al. and Hong et al. teaches the structure of claim 1 and wherein the first material is p-type polysilicon, titanium nitride, tantalum nitride, aluminum, copper or a combination of these materials [¶0030, aluminum, copper, or the like, Hong et al.], and the second material is n-type polysilicon [¶0039, 0043, Hong et al.].
With regards to claim 15, Yeong et al. in further view of Liao et al. and Hong et al. teaches the structure of claim 1 and wherein the first section of the second electrode is coextensive with the second section of the second electrode [¶0073, Hong et al.].
With regards to claim 16, Yeong et al. in further view of Liao et al. and Hong et al. teaches the structure of claim 15 and wherein the ferroelectric layer is disposed fully between the first section of the second electrode and the semiconductor layer, and the ferroelectric layer is disposed fully between the second section of the second electrode and the semiconductor layer [¶0045, Yeong et al.].
With regards to claim 17, Yeong et al. in further view of Liao et al. and Hong et al. teaches the structure of claim 1 and wherein the first section of the second electrode laterally adjoins the second section of the second electrode [¶0073, Hong et al.].
With regards to claim 18, Yeong et al. in further view of Liao et al. and Hong et al. teaches the structure of claim 1 and wherein the second electrode is disposed laterally between the first doped region and the second doped region [Fig. 13, ¶, the second electrode is deposited above the first electrode which has a first and second doped region which are lightly and heavily doped depending on the region, Yeong et al.].
With regards to claim 19, Yeong et al. in further view of Liao et al. and Hong et al. teaches the structure of claim 18 and wherein the ferroelectric layer is disposed laterally between the first doped region and the second doped region [Fig. 13, ¶, the ferroelectric layer is disposed on the first electrode which has a light and heavy doped region, Yeong et al.].
With regards to claim 20, Yeong et al. teaches the method of forming a structure for a ferroelectric capacitive memory device, the method comprising:
Forming a ferroelectric layer on a semiconductor layer [as seen in attached Fig. 13, ¶0038];
Forming a first electrode that includes a first doped region in the semiconductor layer and a second doped layer in the semiconductor layer [as seen in attached Fig. 13, ¶0016],
Yeong et al. doesn’t teach the method of forming a structure with a second electrode that includes a first section and a second section on the ferroelectric layer, and the second section of the second electrode comprising a second material with a second work function that is greater than the first work function of the first material and forming an interconnection that is configured to connect to the first doped region to the second doped region.
Hong et al. teaches the method of forming a second electrode that includes a first section (B as seen in attached Fig. 6) and a second section (A as seen in attached Fig. 6) on the ferroelectric layer, and the second section of the second electrode comprises a second material with a second work function that is greater than the first work function of the first material [¶¶0027, 0029, and 0090, the ferroelectric layer is seen to be 108a and 106 with 106 containing the ferroelectric material];
It would have been obvious to a person with ordinary skill in the art to use the teachings of Hong et al. in Yeong et al. to form the second electrode on a ferroelectric layer because the ferroelectric layer may have a hysteresis characteristic which would be good in enhancing the stability of the structure and with the second electrode being formed on the ferroelectric layer, then the electrode would function with greater efficiency and less leakage.
Yeong et al. in view of Hong et al. doesn’t disclose the method of forming an interconnection that is configured to connect the first doped region to the second doped region.
Liao et al. teaches forming an interconnection that is configured to connect the first doped region to the second doped region [218 Fig. 1, ¶0044].
It would have been obvious for a person with ordinary skill in the art before the filing date of the invention to incorporate the teachings of Liao et al. in the combined device of Yeong et al. in view of Hong et al. because the inclusion of an interconnection would allow for better energy efficiency and better performance of the device.
Allowable Subject Matter
Claims 7-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Relevant Prior Art
Hirano et al. (US 20020008263 A1) also showcases a base structure of a similar ferroelectric memory device that has interconnects which could be combined with the other prior arts in the rejection.
Conclusion
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/NOOR MOHAMMAD ISMAIL TAHIR/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893